Merge pull request #287 from cklarhorst/master

add LPDDR module
2021-11-29 08:34:21 +01:00 · 2021-11-29 08:34:21 +01:00 · 5b233742a4
parent 2113ecfba8 8226dca898
commit 5b233742a4
1 changed files with 10 additions and 0 deletions
--- a/litedram/modules.py
+++ b/litedram/modules.py
@ -572,6 +572,16 @@ class MT46H32M16(LPDDRModule):
    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)}

+class MT46H64M16(LPDDRModule):
+    # geometry
+    nbanks = 4
+    nrows  = 16384
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)}
+
+
 class MT46H32M32(LPDDRModule):
    # geometry
    nbanks = 4