gw2ddrphy: Add TCLK_SOURCE on DQS's OSER4_MEM.

2022-09-08 10:49:54 +02:00 · 2022-09-08 10:49:54 +02:00 · 5b72d1a34a
parent ab9aec9129
commit 5b72d1a34a
1 changed files with 1 additions and 0 deletions
--- a/litedram/phy/gw2ddrphy.py
+++ b/litedram/phy/gw2ddrphy.py
@ -319,6 +319,7 @@ class GW2DDRPHY(Module, AutoCSR):
            dqs_o_oen = Signal()
            self.specials += [
                Instance("OSER4_MEM",
+                    p_TCLK_SOURCE = "DQSW",
                    i_RESET = ResetSignal("sys"),
                    i_PCLK  = ClockSignal("sys"),
                    i_FCLK  = ClockSignal("sys2x"),