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bench/targets: simplify BIST integration using new add_sdram with_bist parameter.

This commit is contained in:
Florent Kermarrec 2020-11-06 10:34:26 +01:00
parent 51b8eb1f82
commit 5cfdf77654
5 changed files with 22 additions and 52 deletions
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14
bench/arty.py
View File

@ -82,18 +82,12 @@ class BenchSoC(SoCCore):
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"]
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
with_bist = with_bist,
)
# BIST -------------------------------------------------------------------------------------
from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
self.add_csr("sdram_generator")
self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
self.add_csr("sdram_checker")
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")

14
bench/genesys2.py
View File

@ -80,18 +80,12 @@ class BenchSoC(SoCCore):
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"]
phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
with_bist = with_bist,
)
# BIST -------------------------------------------------------------------------------------
from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
self.add_csr("sdram_generator")
self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
self.add_csr("sdram_checker")
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")

14
bench/kc705.py
View File

@ -80,18 +80,12 @@ class BenchSoC(SoCCore):
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"]
phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
with_bist = with_bist,
)
# BIST -------------------------------------------------------------------------------------
from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
self.add_csr("sdram_generator")
self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
self.add_csr("sdram_checker")
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")

16
bench/kcu105.py
View File

@ -92,19 +92,13 @@ class BenchSoC(SoCCore):
iodelay_clk_freq = 200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = EDY4016A(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = 0x40000000,
phy = self.ddrphy,
module = EDY4016A(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = 0x40000000,
with_bist = with_bist,
)
# BIST -------------------------------------------------------------------------------------
from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
self.add_csr("sdram_generator")
self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
self.add_csr("sdram_checker")
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")

16
bench/xcu1525.py
View File

@ -88,21 +88,15 @@ class BenchSoC(SoCCore):
iodelay_clk_freq = 500e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT40A512M8(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = 0x40000000,
phy = self.ddrphy,
module = MT40A512M8(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = 0x40000000,
with_bist = with_bist,
)
# Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions.
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]")
# BIST -------------------------------------------------------------------------------------
from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
self.add_csr("sdram_generator")
self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
self.add_csr("sdram_checker")
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")