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bench/test: Avoid use of ident_version (should fix CI).

This commit is contained in:
Florent Kermarrec 2022-02-15 17:33:31 +01:00
parent e6758539d9
commit 5f722a1513
8 changed files with 5 additions and 13 deletions
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1
bench/arty.py
View File

@ -74,7 +74,6 @@ class BenchSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "LiteDRAM bench on Arty",
ident_version = True,
integrated_rom_size = 0x10000,
integrated_rom_mode = "rw",
uart_name = uart)

1
bench/genesys2.py
View File

@ -66,7 +66,6 @@ class BenchSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "LiteDRAM bench on Genesys2",
ident_version = True,
integrated_rom_size = 0x10000,
integrated_rom_mode = "rw",
uart_name = uart)

1
bench/kc705.py
View File

@ -67,7 +67,6 @@ class BenchSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "LiteDRAM bench on KC705",
ident_version = True,
integrated_rom_size = 0x10000,
integrated_rom_mode = "rw",
uart_name = uart)

1
bench/kcu105.py
View File

@ -83,7 +83,6 @@ class BenchSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "LiteDRAM bench on KCU105",
ident_version = True,
integrated_rom_size = 0x10000,
integrated_rom_mode = "rw",
uart_name = uart)

1
bench/xcu1525.py
View File

@ -79,7 +79,6 @@ class BenchSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "LiteDRAM bench on XCU1525",
ident_version = True,
integrated_rom_size = 0x10000,
integrated_rom_mode = "rw",
uart_name = uart)

1
litedram/phy/lpddr4/simsoc.py
View File

@ -76,7 +76,6 @@ class SimSoC(SoCCore):
super().__init__(platform,
clk_freq = sys_clk_freq,
ident = "LiteX Simulation",
ident_version = True,
cpu_variant = "lite",
**kwargs)

7
litedram/phy/lpddr5/simsoc.py
View File

@ -94,10 +94,9 @@ class SimSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
super().__init__(platform,
clk_freq = sys_clk_freq,
ident = "LiteX Simulation",
ident_version = True,
cpu_variant = "lite",
clk_freq = sys_clk_freq,
ident = "LiteX Simulation",
cpu_variant = "lite",
**kwargs)
# CRG --------------------------------------------------------------------------------------

5
litedram/phy/rpc/simsoc.py
View File

@ -149,9 +149,8 @@ class SimSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "LiteX Simulation",
ident_version = True,
cpu_variant = "lite",
ident = "LiteX Simulation",
cpu_variant = "lite",
**kwargs)
# CRG --------------------------------------------------------------------------------------