bench: Update build directories and add rst in CRG (triggered on CPU reboot).

bench/arty.py

@@ -27,6 +27,7 @@ from liteeth.phy.mii import LiteEthPHYMII
 
 class _CRG(Module, AutoCSR):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys_pll   = ClockDomain()
         self.clock_domains.cd_sys       = ClockDomain()
         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
@@ -50,7 +51,7 @@ class _CRG(Module, AutoCSR):
         self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
 
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
-        self.comb += pll.reset.eq(~main_pll.locked)
+        self.comb += pll.reset.eq(~main_pll.locked | self.rst)
         pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
         pll.create_clkout(self.cd_sys,          sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,        4*sys_clk_freq)
@@ -130,7 +131,7 @@ def main():
     args = parser.parse_args()
 
     soc     = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer)
-    builder = Builder(soc, csr_csv="csr.csv")
+    builder = Builder(soc, output_dir="build/arty", csr_csv="csr.csv")
     builder.build(run=args.build)
 
     if args.load:

bench/genesys2.py

@@ -27,6 +27,7 @@ from liteeth.phy.s7rgmii import LiteEthPHYRGMII
 
 class _CRG(Module, AutoCSR):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys_pll   = ClockDomain()
         self.clock_domains.cd_sys       = ClockDomain()
         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
@@ -45,7 +46,7 @@ class _CRG(Module, AutoCSR):
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 
         self.submodules.pll = pll = S7PLL(speedgrade=-2)
-        self.comb += pll.reset.eq(~main_pll.locked)
+        self.comb += pll.reset.eq(~main_pll.locked | self.rst)
         pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
@@ -124,7 +125,7 @@ def main():
     args = parser.parse_args()
 
     soc     = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer)
-    builder = Builder(soc, csr_csv="csr.csv")
+    builder = Builder(soc, output_dir="build/genesys2", csr_csv="csr.csv")
     builder.build(run=args.build)
 
     if args.load:

bench/kc705.py

@@ -27,6 +27,7 @@ from liteeth.phy import LiteEthPHY
 
 class _CRG(Module, AutoCSR):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys_pll   = ClockDomain()
         self.clock_domains.cd_sys       = ClockDomain()
         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
@@ -45,7 +46,7 @@ class _CRG(Module, AutoCSR):
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 
         self.submodules.pll = pll = S7PLL(speedgrade=-2)
-        self.comb += pll.reset.eq(~main_pll.locked)
+        self.comb += pll.reset.eq(~main_pll.locked | self.rst)
         pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
@@ -124,7 +125,7 @@ def main():
     args = parser.parse_args()
 
     soc     = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer)
-    builder = Builder(soc, csr_csv="csr.csv")
+    builder = Builder(soc, output_dir="build/kc705", csr_csv="csr.csv")
     builder.build(run=args.build)
 
     if args.load:

bench/kcu105.py

@@ -28,6 +28,7 @@ from liteeth.phy.ku_1000basex import KU_1000BASEX
 
 class _CRG(Module, AutoCSR):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys_pll = ClockDomain()
         self.clock_domains.cd_sys     = ClockDomain()
         self.clock_domains.cd_sys4x   = ClockDomain(reset_less=True)
@@ -48,7 +49,7 @@ class _CRG(Module, AutoCSR):
         main_pll.expose_drp()
 
         self.submodules.pll = pll = USMMCM(speedgrade=-2)
-        self.comb += pll.reset.eq(~main_pll.locked)
+        self.comb += pll.reset.eq(~main_pll.locked | self.rst)
         pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
         pll.create_clkout(self.cd_pll4x,  sys_clk_freq*4, buf=None, with_reset=False)
 
@@ -144,7 +145,7 @@ def main():
     args = parser.parse_args()
 
     soc     = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer)
-    builder = Builder(soc, csr_csv="csr.csv")
+    builder = Builder(soc, output_dir="build/kcu105", csr_csv="csr.csv")
     builder.build(run=args.build)
 
     if args.load:

bench/xcu1525.py

@@ -27,6 +27,7 @@ from litedram.phy import usddrphy
 
 class _CRG(Module, AutoCSR):
     def __init__(self, platform, sys_clk_freq, channel):
+        self.rst = Signal()
         self.clock_domains.cd_sys_pll = ClockDomain()
         self.clock_domains.cd_sys     = ClockDomain()
         self.clock_domains.cd_sys4x   = ClockDomain(reset_less=True)
@@ -44,7 +45,7 @@ class _CRG(Module, AutoCSR):
         main_pll.expose_drp()
 
         self.submodules.pll = pll = USPMMCM(speedgrade=-2)
-        self.comb += pll.reset.eq(~main_pll.locked)
+        self.comb += pll.reset.eq(~main_pll.locked | self.rst)
         pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
         pll.create_clkout(self.cd_pll4x,  sys_clk_freq*4, buf=None, with_reset=False)