phy: rename KUSDDRPHY to USDDRPHY since compatible with Kintex/Virtex Ultrascale

README

@@ -27,7 +27,7 @@ PHY:
   - Generic SDRAM PHY (vendor agnostic, tested on Xilinx, Altera, Lattice)
   - Spartan6 DDR/LPDDR/DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
   - Spartan7/Artix7/Kintex7/Virtex7 DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
-  - Kintex Ultrascale DDR3/DDR4 PHY (1:4 frequency ratio)
+  - Kintex/Virtex Ultrascale DDR3/DDR4 PHY (1:4 frequency ratio)
 Core:
   - Fully pipelined, high performance.
   - Configurable commands depth on bankmachines.

litedram/phy/__init__.py

@@ -1,7 +1,7 @@
 from litedram.phy.gensdrphy import GENSDRPHY
 from litedram.phy.s6ddrphy import S6HalfRateDDRPHY, S6QuarterRateDDRPHY
 from litedram.phy.s7ddrphy import V7DDRPHY, K7DDRPHY, A7DDRPHY
-from litedram.phy.kusddrphy import KUSDDRPHY
+from litedram.phy.usddrphy import USDDRPHY
 
 # backward compatibility (remove when no longer needed)
 from litedram.phy import s7ddrphy as a7ddrphy

litedram/phy/usddrphy.py

@@ -1,4 +1,4 @@
-# 1:4 frequency-ratio DDR3/DDR4 PHY for Kintex Ultrascale
+# 1:4 frequency-ratio DDR3/DDR4 PHY for Kintex/Virtex Ultrascale
 # DDR3: 800, 1066, 1333 and 1600 MT/s
 # DDR4: 1600 MT/s
 
@@ -57,7 +57,7 @@ class DDR4DFIMux(Module):
             ]
 
 
-class KUSDDRPHY(Module, AutoCSR):
+class USDDRPHY(Module, AutoCSR):
     def __init__(self, pads, memtype="DDR3", sys_clk_freq=100e6):
         tck = 2/(2*4*sys_clk_freq)
         addressbits = len(pads.a)