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phy/kusddrphy: add TODO

This commit is contained in:
Florent Kermarrec 2017-02-10 13:05:49 +01:00
parent ac43e0118e
commit 63434324e6
1 changed files with 6 additions and 1 deletions
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7
litedram/phy/kusddrphy.py
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@ -9,6 +9,11 @@ from litedram.common import PhySettings
from litedram.phy.dfi import * from litedram.phy.dfi import *
from litedram.phy.bitslip import BitSlip from litedram.phy.bitslip import BitSlip
# TODO:
# - verify read_latency in simulation (OSERDESE3/ISERDESE3)
# - verify initial p_DELAY_VALUE on ODELAYE3/IDELAYE3
# - simulate with Micron's model
# - test on board
class KUSDDRPHY(Module, AutoCSR): class KUSDDRPHY(Module, AutoCSR):
def __init__(self, pads): def __init__(self, pads):
@ -275,7 +280,7 @@ class KUSDDRPHY(Module, AutoCSR):
# 2 cycles through OSERDESE3 TODO: verify latency # 2 cycles through OSERDESE3 TODO: verify latency
# 2 cycles CAS # 2 cycles CAS
# 2 cycles through ISERDESE3 TODO: verify latency # 2 cycles through ISERDESE3 TODO: verify latency
# 2 cycles through Bitslip # 2 cycles through BitSlip
rddata_en = self.dfi.phases[self.settings.rdphase].rddata_en rddata_en = self.dfi.phases[self.settings.rdphase].rddata_en
for i in range(8-1): for i in range(8-1):
n_rddata_en = Signal() n_rddata_en = Signal()