examples/litedram_gen: allow direct access to CSR (I/O) registers

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
[florent@enjoy-digital.fr: use add_csr_master, fix csr_port.dat_r typo]

examples/arty_config.py

@@ -32,4 +32,7 @@ core_config = {
     "user_ports_nb":       2,     # Number of user ports
     "user_ports_type":     "axi", # Type of ports (axi, native)
     "user_ports_id_width": 32,    # AXI identifier width
+
+    # CSR Port -----------------------------------------------------------------
+    "expose_csr_port": "no", # expose access to CSR (I/O) ports
 }

examples/genesys2_config.py

@@ -32,4 +32,7 @@ core_config = {
     "user_ports_nb":       2,     # Number of user ports
     "user_ports_type":     "axi", # Type of ports (axi, native)
     "user_ports_id_width": 32,    # AXI identifier width
+
+    # CSR Port -----------------------------------------------------------------
+    "expose_csr_port": "no", # expose access to CSR (I/O) ports
 }

examples/litedram_gen.py

@@ -14,6 +14,7 @@ from litex.soc.cores.clock import *
 from litedram.core.controller import ControllerSettings
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.interconnect import csr_bus
 from litex.soc.cores.uart import *
 
 from litedram.frontend.axi import *
@@ -71,6 +72,16 @@ def get_dram_ios(core_config):
         ),
     ]
 
+def get_csr_ios(aw, dw):
+    return [
+        ("csr_port", 0,
+            Subsignal("adr", Pins(aw)),
+            Subsignal("we", Pins(1)),
+            Subsignal("dat_w", Pins(dw)),
+            Subsignal("dat_r", Pins(dw))
+        ),
+    ]
+
 def get_native_user_port_ios(_id, aw, dw):
     return [
         ("user_port", _id,
@@ -234,6 +245,20 @@ class LiteDRAMCore(SoCSDRAM):
             platform.request("init_error").eq(self.ddrctrl.init_error.storage)
         ]
 
+        # CSR port
+        if core_config.get("expose_csr_port", "no") == "yes":
+            csr_port = csr_bus.Interface(self.csr_address_width, self.csr_data_width)
+            self.add_csr_master(csr_port)
+            platform.add_extension(get_csr_ios(self.csr_address_width,
+                                               self.csr_data_width))
+            _csr_port_io = platform.request("csr_port", 0)
+            self.comb += [
+                csr_port.adr.eq(_csr_port_io.adr),
+                csr_port.we.eq(_csr_port_io.we),
+                csr_port.dat_w.eq(_csr_port_io.dat_w),
+                _csr_port_io.dat_r.eq(csr_port.dat_r),
+            ]
+
         # user port
         self.comb += [
             platform.request("user_clk").eq(ClockSignal()),

examples/nexys4ddr_config.py

@@ -27,4 +27,7 @@ core_config = {
     "user_ports_nb":       2,     # Number of user ports
     "user_ports_type":     "axi", # Type of ports (axi, native)
     "user_ports_id_width": 32,    # AXI identifier width
+
+    # CSR Port -----------------------------------------------------------------
+    "expose_csr_port": "no", # expose access to CSR (I/O) ports
 }