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litedram/common: add cl/cwl values for DDR4 data rates from 1333MT/s to 2666MT/s.

This commit is contained in:
Florent Kermarrec 2020-09-29 19:46:39 +02:00
parent c2d1cf358b
commit 68e9a02a55
1 changed files with 5 additions and 0 deletions
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5
litedram/common.py
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@ -40,7 +40,12 @@ def get_cl_cw(memtype, tck):
f_to_cl_cwl[1333e6] = (10, 7)
f_to_cl_cwl[1600e6] = (11, 8)
elif memtype == "DDR4":
f_to_cl_cwl[1333e6] = (9, 9)
f_to_cl_cwl[1600e6] = (11, 9)
f_to_cl_cwl[1866e6] = (13, 10)
f_to_cl_cwl[2133e6] = (15, 11)
f_to_cl_cwl[2400e6] = (16, 12)
f_to_cl_cwl[2666e6] = (18, 14)
else:
raise ValueError
for f, (cl, cwl) in f_to_cl_cwl.items():