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add board tuning parameters

This commit is contained in:
bunnie 2018-08-21 09:18:00 +02:00 committed by Florent Kermarrec
parent 9a57c4e88c
commit 697eaafc4c
2 changed files with 27 additions and 6 deletions
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8
litedram/common.py
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@ -10,7 +10,8 @@ class PhySettings:
nphases, nphases,
rdphase, wrphase, rdphase, wrphase,
rdcmdphase, wrcmdphase, rdcmdphase, wrcmdphase,
cl, read_latency, write_latency, cwl=0): cl, read_latency, write_latency, cwl=0,
rtt_nom='40ohm', drive_strength='40ohm', dynamic_odt='60ohm'):
self.memtype = memtype self.memtype = memtype
self.dfi_databits = dfi_databits self.dfi_databits = dfi_databits
@ -25,6 +26,11 @@ class PhySettings:
self.write_latency = write_latency self.write_latency = write_latency
self.cwl = cwl self.cwl = cwl
# board tuning parameters
self.rtt_nom = rtt_nom
self.drive_strength = drive_strength
self.dynamic_odt = dynamic_odt
class GeomSettings: class GeomSettings:
def __init__(self, bankbits, rowbits, colbits): def __init__(self, bankbits, rowbits, colbits):

25
litedram/sdram_init.py
View File

@ -24,10 +24,8 @@ static void command_p{n}(int cmd)
r += """ r += """
#define sdram_dfii_pird_address_write(X) sdram_dfii_pi{rdphase}_address_write(X) #define sdram_dfii_pird_address_write(X) sdram_dfii_pi{rdphase}_address_write(X)
#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi{wrphase}_address_write(X) #define sdram_dfii_piwr_address_write(X) sdram_dfii_pi{wrphase}_address_write(X)
#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi{rdphase}_baddress_write(X) #define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi{rdphase}_baddress_write(X)
#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi{wrphase}_baddress_write(X) #define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi{wrphase}_baddress_write(X)
#define command_prd(X) command_p{rdphase}(X) #define command_prd(X) command_p{rdphase}(X)
#define command_pwr(X) command_p{wrphase}(X) #define command_pwr(X) command_p{wrphase}(X)
""".format(rdphase=str(sdram_phy_settings.rdphase), wrphase=str(sdram_phy_settings.wrphase)) """.format(rdphase=str(sdram_phy_settings.rdphase), wrphase=str(sdram_phy_settings.wrphase))
@ -190,9 +188,26 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
mr2 |= rtt_wr << 9 mr2 |= rtt_wr << 9
return mr2 return mr2
mr0 = format_mr0(bl, cl, 8, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK) z_to_rttnom = {
mr1 = format_mr1(1, 1) # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm) 'disabled' : 0,
mr2 = format_mr2(sdram_phy_settings.cwl, 2) # Rtt(WR) RZQ/4 '60ohm' : 1,
'120ohm' : 2,
'40ohm' : 3,
'20ohm' : 4,
'30ohm' : 5
}
z_to_output_drive_strength = {
'40ohm' : 0,
'34ohm' : 1,
}
z_to_dynamic_odt = {
'disabled' : 0,
'60ohm' : 1,
'120ohm' : 2,
}
mr0 = format_mr0(bl, cl, 14, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
mr1 = format_mr1(z_to_output_drive_strength[sdram_phy_settings.drive_strength], z_to_rttnom[sdram_phy_settings.rtt_nom])
mr2 = format_mr2(sdram_phy_settings.cwl, z_to_dynamic_odt[sdram_phy_settings.dynamic_odt])
mr3 = 0 mr3 = 0
init_sequence = [ init_sequence = [