add board tuning parameters
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@ -10,7 +10,8 @@ class PhySettings:
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nphases,
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rdphase, wrphase,
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rdcmdphase, wrcmdphase,
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cl, read_latency, write_latency, cwl=0):
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cl, read_latency, write_latency, cwl=0,
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rtt_nom='40ohm', drive_strength='40ohm', dynamic_odt='60ohm'):
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self.memtype = memtype
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self.dfi_databits = dfi_databits
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@ -25,6 +26,11 @@ class PhySettings:
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self.write_latency = write_latency
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self.cwl = cwl
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# board tuning parameters
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self.rtt_nom = rtt_nom
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self.drive_strength = drive_strength
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self.dynamic_odt = dynamic_odt
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class GeomSettings:
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def __init__(self, bankbits, rowbits, colbits):
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@ -24,10 +24,8 @@ static void command_p{n}(int cmd)
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r += """
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#define sdram_dfii_pird_address_write(X) sdram_dfii_pi{rdphase}_address_write(X)
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#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi{wrphase}_address_write(X)
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#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi{rdphase}_baddress_write(X)
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#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi{wrphase}_baddress_write(X)
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#define command_prd(X) command_p{rdphase}(X)
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#define command_pwr(X) command_p{wrphase}(X)
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""".format(rdphase=str(sdram_phy_settings.rdphase), wrphase=str(sdram_phy_settings.wrphase))
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@ -190,9 +188,26 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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mr2 |= rtt_wr << 9
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return mr2
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mr0 = format_mr0(bl, cl, 8, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
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mr1 = format_mr1(1, 1) # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm)
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mr2 = format_mr2(sdram_phy_settings.cwl, 2) # Rtt(WR) RZQ/4
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z_to_rttnom = {
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'disabled' : 0,
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'60ohm' : 1,
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'120ohm' : 2,
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'40ohm' : 3,
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'20ohm' : 4,
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'30ohm' : 5
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}
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z_to_output_drive_strength = {
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'40ohm' : 0,
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'34ohm' : 1,
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}
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z_to_dynamic_odt = {
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'disabled' : 0,
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'60ohm' : 1,
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'120ohm' : 2,
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}
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mr0 = format_mr0(bl, cl, 14, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
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mr1 = format_mr1(z_to_output_drive_strength[sdram_phy_settings.drive_strength], z_to_rttnom[sdram_phy_settings.rtt_nom])
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mr2 = format_mr2(sdram_phy_settings.cwl, z_to_dynamic_odt[sdram_phy_settings.dynamic_odt])
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mr3 = 0
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init_sequence = [
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