Merge pull request #62 from daveshah1/AS4C32M16

modules: Add AS4C32M16 32Mx16 SDRAM
2018-11-06 14:50:14 +01:00 · 2018-11-06 14:50:14 +01:00 · 69ea8668d0
parent b41fe61b2a 3a5d45bd5e
commit 69ea8668d0
1 changed files with 11 additions and 0 deletions
--- a/litedram/modules.py
+++ b/litedram/modules.py
@ -136,6 +136,17 @@ class AS4C16M16(SDRAMModule):
    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=12, tRFC=60, tFAW=None, tRAS=None)}


+class AS4C32M16(SDRAMModule):
+    memtype = "SDR"
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=12, tRFC=60, tFAW=None, tRAS=None)}
+
+
 # DDR
 class MT46V32M16(SDRAMModule):
    memtype = "DDR"