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Fix DDR2 and below compilation failure

This commit is contained in:
2018-10-01 19:35:20 -04:00
parent 70516c40bf
commit 69eaf844e8
1 changed files with 4 additions and 1 deletions
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3
litedram/common.py
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@ -24,6 +24,9 @@ class PhySettings:
self.cl = cl self.cl = cl
self.read_latency = read_latency self.read_latency = read_latency
self.write_latency = write_latency self.write_latency = write_latency
if cwl is None:
self.cwl = cl
else:
self.cwl = cwl self.cwl = cwl
# Optional DDR3 electrical settings # Optional DDR3 electrical settings