Fix DDR2 and below compilation failure

2018-10-01 19:35:20 -04:00 · 2018-10-01 19:35:20 -04:00 · 69eaf844e8
parent 70516c40bf
commit 69eaf844e8
1 changed files with 4 additions and 1 deletions
--- a/litedram/common.py
+++ b/litedram/common.py
@ -24,6 +24,9 @@ class PhySettings:
        self.cl = cl
        self.read_latency = read_latency
        self.write_latency = write_latency
+        if cwl is None:
+            self.cwl = cl
+        else:
            self.cwl = cwl

    # Optional DDR3 electrical settings