init: Simplify SDRAM_PHY_MODULES define: this is just SDRAM_PHY_DATABITS/8.
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@ -701,24 +701,20 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
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r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
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# Define number of modules/delays/bitslips
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r += "#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8\n"
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if phytype in ["USDDRPHY", "USPDDRPHY"]:
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r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n"
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r += "#define SDRAM_PHY_DELAYS 512\n"
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r += "#define SDRAM_PHY_BITSLIPS 8\n"
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elif phytype in ["A7DDRPHY", "K7DDRPHY", "V7DDRPHY"]:
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r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n"
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r += "#define SDRAM_PHY_DELAYS 32\n"
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r += "#define SDRAM_PHY_BITSLIPS 8\n"
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elif phytype in ["A7LPDDR4PHY", "K7LPDDR4PHY", "V7LPDDR4PHY"]:
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r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n"
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r += "#define SDRAM_PHY_DELAYS 32\n"
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r += "#define SDRAM_PHY_BITSLIPS 16\n"
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elif phytype in ["ECP5DDRPHY"]:
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r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/4\n"
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r += "#define SDRAM_PHY_DELAYS 8\n"
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r += "#define SDRAM_PHY_BITSLIPS 4\n"
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elif phytype in ["LPDDR4SIMPHY"]:
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r += "#define SDRAM_PHY_MODULES 2\n"
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r += "#define SDRAM_PHY_DELAYS 1\n"
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r += "#define SDRAM_PHY_BITSLIPS 16\n"
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