Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #274 from teknoman117/alchitry-ram-modules 

Add AS4C128M16 DDR3L-1600 ram
This commit is contained in:
enjoy-digital 2021-09-09 11:53:42 +02:00 committed by GitHub
parent db879ae3f7 cbb699ce52
commit 6a82042fee
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 12 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
litedram/modules.py
View File

@ -618,6 +618,18 @@ class P3R1GE4JGF(DDR2Module):
class DDR3Module(SDRAMModule): memtype = "DDR3"
class DDR3RegisteredModule(SDRAMRegisteredModule): memtype = "DDR3"
class AS4C128M16(DDR3Module):
# geometry
nbanks = 8
nrows = 16384
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6), tZQCS=(64, 80))
speedgrade_timings = {
"1600": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=13.75, tRFC=(160, None), tFAW=(None, 40), tRAS=35),
}
speedgrade_timings["default"] = speedgrade_timings["1600"]
class MT41K64M16(DDR3Module):
# geometry
nbanks = 8