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Prevent spurious precharge all commands caused by leaving A10 asserted during precharge

This commit is contained in:
2018-05-03 14:29:39 -04:00
parent d0fcfb172f
commit 6b0d5ceeae
1 changed files with 13 additions and 13 deletions
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26
litedram/core/bankmachine.py
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@ -68,19 +68,6 @@ class BankMachine(Module):
req.lock.eq(cmd_buffer.source.valid), req.lock.eq(cmd_buffer.source.valid),
] ]
#Set row change buffer
self.comb += [
rowchg_buffer.sink.differentRow.eq(slicer.row(req.adr) != row_last),
rowchg_buffer.sink.valid.eq(cmd_buffer.source.valid & cmd_buffer.sink.valid & cmd_buffer.sink.ready),
rowchg_buffer.source.ready.eq(cmd_buffer.source.ready),
auto_precharge.eq(rowchg_buffer.source.differentRow & rowchg_buffer.source.valid),
]
self.sync += [
If(cmd_buffer.sink.valid & cmd_buffer.sink.ready,
row_last.eq(slicer.row(req.adr))
)
]
# Row tracking # Row tracking
has_openrow = Signal() has_openrow = Signal()
openrow = Signal(settings.geom.rowbits, reset_less=True) openrow = Signal(settings.geom.rowbits, reset_less=True)
@ -96,6 +83,19 @@ class BankMachine(Module):
openrow.eq(slicer.row(cmd_buffer.source.adr)) openrow.eq(slicer.row(cmd_buffer.source.adr))
) )
#Set row change buffer
self.comb += [
rowchg_buffer.sink.differentRow.eq(slicer.row(req.adr) != row_last),
rowchg_buffer.sink.valid.eq(cmd_buffer.source.valid & cmd_buffer.sink.valid & cmd_buffer.sink.ready),
rowchg_buffer.source.ready.eq(cmd_buffer.source.ready),
auto_precharge.eq(rowchg_buffer.source.differentRow & rowchg_buffer.source.valid & (track_close == 0)),
]
self.sync += [
If(cmd_buffer.sink.valid & cmd_buffer.sink.ready,
row_last.eq(slicer.row(req.adr))
)
]
# Address generation # Address generation
sel_row_adr = Signal() sel_row_adr = Signal()
self.comb += [ self.comb += [