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Adding tCCD for DDR2 modules.

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This commit is contained in:
Tim 'mithro' Ansell 2018-10-01 18:49:10 -07:00
parent 208f5562d1
commit 6c7a804986
1 changed files with 3 additions and 0 deletions
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3
litedram/modules.py
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@ -194,6 +194,7 @@ class MT47H128M8(SDRAMModule):
# speedgrade invariant timings # speedgrade invariant timings
tREFI = 64e6/8192 tREFI = 64e6/8192
tWTR = (None, 7.5) tWTR = (None, 7.5)
tCCD = (2, None)
# speedgrade related timings # speedgrade related timings
tRP = 15 tRP = 15
tRCD = 15 tRCD = 15
@ -210,6 +211,7 @@ class MT47H64M16(SDRAMModule):
# speedgrade invariant timings # speedgrade invariant timings
tREFI = 64e6/8192 tREFI = 64e6/8192
tWTR = (None, 7.5) tWTR = (None, 7.5)
tCCD = (2, None)
# speedgrade related timings # speedgrade related timings
tRP = 15 tRP = 15
tRCD = 15 tRCD = 15
@ -227,6 +229,7 @@ class P3R1GE4JGF(SDRAMModule):
# speedgrade invariant timings # speedgrade invariant timings
tREFI = 64e6/8192 tREFI = 64e6/8192
tWTR = (None, 7.5) tWTR = (None, 7.5)
tCCD = (2, None)
# speedgrade related timings # speedgrade related timings
tRP = 12.5 tRP = 12.5
tRCD = 12.5 tRCD = 12.5