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test/reference: update.

This commit is contained in:
Florent Kermarrec 2020-09-30 18:06:48 +02:00
parent 18e8f5c565
commit 6d063b196c
3 changed files with 6 additions and 24 deletions
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10
test/reference/ddr3_init.h
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@ -20,6 +20,8 @@
#define SDRAM_PHY_DATABITS 64 #define SDRAM_PHY_DATABITS 64
#define SDRAM_PHY_PHASES 4 #define SDRAM_PHY_PHASES 4
#define SDRAM_PHY_CMD_LATENCY 1 #define SDRAM_PHY_CMD_LATENCY 1
#define SDRAM_PHY_RDPHASE 1
#define SDRAM_PHY_WRPHASE 1
#define SDRAM_PHY_WRITE_LEVELING_CAPABLE #define SDRAM_PHY_WRITE_LEVELING_CAPABLE
#define SDRAM_PHY_READ_LEVELING_CAPABLE #define SDRAM_PHY_READ_LEVELING_CAPABLE
#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2 #define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2
@ -49,14 +51,6 @@ __attribute__((unused)) static void command_p3(int cmd)
sdram_dfii_pi3_command_issue_write(1); sdram_dfii_pi3_command_issue_write(1);
} }
#define sdram_dfii_pird_address_write(X) sdram_dfii_pi1_address_write(X)
#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi1_address_write(X)
#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi1_baddress_write(X)
#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi1_baddress_write(X)
#define command_prd(X) command_p1(X)
#define command_pwr(X) command_p1(X)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = { const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = {

10
test/reference/ddr4_init.h
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@ -20,6 +20,8 @@
#define SDRAM_PHY_DATABITS 64 #define SDRAM_PHY_DATABITS 64
#define SDRAM_PHY_PHASES 4 #define SDRAM_PHY_PHASES 4
#define SDRAM_PHY_CMD_LATENCY 1 #define SDRAM_PHY_CMD_LATENCY 1
#define SDRAM_PHY_RDPHASE 3
#define SDRAM_PHY_WRPHASE 2
#define SDRAM_PHY_WRITE_LEVELING_CAPABLE #define SDRAM_PHY_WRITE_LEVELING_CAPABLE
#define SDRAM_PHY_WRITE_LEVELING_REINIT #define SDRAM_PHY_WRITE_LEVELING_REINIT
#define SDRAM_PHY_READ_LEVELING_CAPABLE #define SDRAM_PHY_READ_LEVELING_CAPABLE
@ -50,14 +52,6 @@ __attribute__((unused)) static void command_p3(int cmd)
sdram_dfii_pi3_command_issue_write(1); sdram_dfii_pi3_command_issue_write(1);
} }
#define sdram_dfii_pird_address_write(X) sdram_dfii_pi3_address_write(X)
#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi2_address_write(X)
#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi3_baddress_write(X)
#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi2_baddress_write(X)
#define command_prd(X) command_p3(X)
#define command_pwr(X) command_p2(X)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = { const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = {

10
test/reference/sdr_init.h
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@ -19,6 +19,8 @@
#define SDRAM_PHY_XDR 1 #define SDRAM_PHY_XDR 1
#define SDRAM_PHY_DATABITS 16 #define SDRAM_PHY_DATABITS 16
#define SDRAM_PHY_PHASES 1 #define SDRAM_PHY_PHASES 1
#define SDRAM_PHY_RDPHASE 0
#define SDRAM_PHY_WRPHASE 0
static void cdelay(int i); static void cdelay(int i);
@ -28,14 +30,6 @@ __attribute__((unused)) static void command_p0(int cmd)
sdram_dfii_pi0_command_issue_write(1); sdram_dfii_pi0_command_issue_write(1);
} }
#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X)
#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi0_address_write(X)
#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi0_baddress_write(X)
#define command_prd(X) command_p0(X)
#define command_pwr(X) command_p0(X)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = { const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = {