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README: update

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Florent Kermarrec 2019-04-27 09:46:59 +02:00
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@ -3,10 +3,10 @@
/ /__/ / __/ -_) // / , _/ __ |/ /|_/ / / /__/ / __/ -_) // / , _/ __ |/ /|_/ /
/____/_/\__/\__/____/_/|_/_/ |_/_/ /_/ /____/_/\__/\__/____/_/|_/_/ |_/_/ /_/
Copyright 2015-2018 / EnjoyDigital Copyright 2015-2019 / EnjoyDigital
A small footprint and configurable DRAM core A small footprint and configurable DRAM core
powered by LiteX & Migen powered by Migen & LiteX
[> Intro [> Intro
-------- --------
@ -28,12 +28,13 @@ PHY:
- Spartan6 DDR/LPDDR/DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio) - Spartan6 DDR/LPDDR/DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
- Spartan7/Artix7/Kintex7/Virtex7 DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio) - Spartan7/Artix7/Kintex7/Virtex7 DDR2/DDR3 PHY (1:2 or 1:4 frequency ratio)
- Kintex/Virtex Ultrascale DDR3/DDR4 PHY (1:4 frequency ratio) - Kintex/Virtex Ultrascale DDR3/DDR4 PHY (1:4 frequency ratio)
- ECP5 DDR3 PHY (1:4 frequency ratio)
Core: Core:
- Fully pipelined, high performance. - Fully pipelined, high performance.
- Configurable commands depth on bankmachines. - Configurable commands depth on bankmachines.
- Auto-Precharge. - Auto-Precharge.
Frontend: Frontend:
- Configurable crossbar (simply declare your crossbar and use crossbar.get_port() to add a new port!) - Configurable crossbar (simply use crossbar.get_port() to add a new port!)
- Ports arbitration transparent to the user. - Ports arbitration transparent to the user.
- Native, AXI-MM or Wishbone user interface. - Native, AXI-MM or Wishbone user interface.
- DMA reader/writer. - DMA reader/writer.
@ -44,13 +45,14 @@ Frontend:
--------------- ---------------
LiteDRAM is already used in commercial and open-source designs: LiteDRAM is already used in commercial and open-source designs:
- HDMI2USB: http://hdmi2usb.tv/home/ - HDMI2USB: http://hdmi2usb.tv/home/
- NeTV2: https://www.crowdsupply.com/alphamax/netv2
- USBSniffer: http://blog.lambdaconcept.com/doku.php?id=products:usb_sniffer
- and others commercial designs... - and others commercial designs...
[> Possible improvements [> Possible improvements
------------------------ ------------------------
- add Avalon-ST interface. - add Avalon-ST interface.
- add support for Altera PHYs. - add support for Altera devices.
- add support for Lattice PHYs.
- add more documentation - add more documentation
- ... See below Support and consulting :) - ... See below Support and consulting :)
@ -59,16 +61,15 @@ enjoy-digital.fr.
[> Getting started [> Getting started
------------------ ------------------
1. Install Python 3.5, Migen and FPGA vendor's development tools. 0. Install Python 3.5+ and FPGA vendor's development tools.
Get Migen from: https://github.com/m-labs/migen
2. Obtain LiteX and install it: 1. Install Migen/LiteX and the LiteX's cores:
git clone https://github.com/enjoy-digital/litex --recursive wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
cd litex ./litex_setup.py init install
python3 setup.py develop Later, if you need to update all repositories:
cd .. ./litex_setup.py update
3. TODO: add/describe examples 2. TODO: add/describe examples
[> Tests [> Tests
-------- --------