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core/bankmachine/write to precharge: indicate that AL=0

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This commit is contained in:
Florent Kermarrec 2018-09-25 21:04:19 +02:00
parent 869c8ee618
commit 6e10daed58
1 changed files with 1 additions and 1 deletions
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litedram/core/bankmachine.py
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@ -86,7 +86,7 @@ class BankMachine(Module):
# Respect write-to-precharge specification
write_latency = math.ceil(settings.phy.cwl / settings.phy.nphases)
precharge_time = write_latency + settings.timing.tWR - 1 + settings.timing.tCCD
precharge_time = write_latency + settings.timing.tWR - 1 + settings.timing.tCCD # AL=0
precharge_timer = WaitTimer(precharge_time)
self.submodules += precharge_timer
self.comb += precharge_timer.wait.eq(~(cmd.valid & cmd.ready & cmd.is_write))