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phy/s7ddrphy: replace dm/dq delays with BitSlip.

This commit is contained in:
Florent Kermarrec 2020-10-08 16:57:12 +02:00
parent c16628531a
commit 6e8d37c873
1 changed files with 11 additions and 9 deletions
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20
litedram/phy/s7ddrphy.py
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@ -98,7 +98,7 @@ class S7DDRPHY(Module, AutoCSR):
cl = cl, cl = cl,
cwl = cwl, cwl = cwl,
read_latency = cl_sys_latency + 6, read_latency = cl_sys_latency + 6,
write_latency = cwl_sys_latency - 1, write_latency = cwl_sys_latency - 2,
cmd_latency = cmd_latency, cmd_latency = cmd_latency,
cmd_delay = cmd_delay, cmd_delay = cmd_delay,
) )
@ -264,9 +264,10 @@ class S7DDRPHY(Module, AutoCSR):
# DM --------------------------------------------------------------------------------------- # DM ---------------------------------------------------------------------------------------
for i in range(databits//8): for i in range(databits//8):
dm_o_nodelay = Signal() dm_o_nodelay = Signal()
_dm = Cat(*[dfi.phases[n//2].wrdata_mask[n%2*databits//8+i] for n in range(8)]) dm_o_bitslip = BitSlip(8,
dm = Signal(8) i = Cat(*[dfi.phases[n//2].wrdata_mask[n%2*databits//8+i] for n in range(8)]),
self.sync += dm.eq(_dm) cycles = 1)
self.submodules += dm_o_bitslip
self.specials += Instance("OSERDESE2", self.specials += Instance("OSERDESE2",
p_SERDES_MODE = "MASTER", p_SERDES_MODE = "MASTER",
p_DATA_WIDTH = 2*nphases, p_DATA_WIDTH = 2*nphases,
@ -276,7 +277,7 @@ class S7DDRPHY(Module, AutoCSR):
i_RST = ResetSignal() | self._rst.storage, i_RST = ResetSignal() | self._rst.storage,
i_CLK = ClockSignal(ddr_clk), i_CLK = ClockSignal(ddr_clk),
i_CLKDIV = ClockSignal(), i_CLKDIV = ClockSignal(),
**{f"i_D{n+1}": dm[n] for n in range(8)}, **{f"i_D{n+1}": dm_o_bitslip.o[n] for n in range(8)},
i_OCE = 1, i_OCE = 1,
o_OQ = dm_o_nodelay if with_odelay else pads.dm[i], o_OQ = dm_o_nodelay if with_odelay else pads.dm[i],
) )
@ -311,9 +312,10 @@ class S7DDRPHY(Module, AutoCSR):
dq_i_delayed = Signal() dq_i_delayed = Signal()
dq_t = Signal() dq_t = Signal()
dq_i_data = Signal(8) dq_i_data = Signal(8)
_dq = Cat(*[dfi.phases[n//2].wrdata[n%2*databits+i] for n in range(8)]) dq_o_bitslip = BitSlip(8,
dq = Signal(8) i = Cat(*[dfi.phases[n//2].wrdata[n%2*databits+i] for n in range(8)]),
self.sync += dq.eq(_dq) cycles = 1)
self.submodules += dq_o_bitslip
self.specials += Instance("OSERDESE2", self.specials += Instance("OSERDESE2",
p_SERDES_MODE = "MASTER", p_SERDES_MODE = "MASTER",
p_DATA_WIDTH = 2*nphases, p_DATA_WIDTH = 2*nphases,
@ -323,7 +325,7 @@ class S7DDRPHY(Module, AutoCSR):
i_RST = ResetSignal() | self._rst.storage, i_RST = ResetSignal() | self._rst.storage,
i_CLK = ClockSignal(ddr_clk), i_CLK = ClockSignal(ddr_clk),
i_CLKDIV = ClockSignal(), i_CLKDIV = ClockSignal(),
**{f"i_D{n+1}": dq[n] for n in range(8)}, **{f"i_D{n+1}": dq_o_bitslip.o[n] for n in range(8)},
i_TCE = 1, i_TCE = 1,
i_T1 = ~dq_oe_delay.output, i_T1 = ~dq_oe_delay.output,
o_TQ = dq_t, o_TQ = dq_t,