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phy/s7ddrphy: Add +1 to CL in MR register to increase sys_clk_freq range. 

Allow successful DDR3 calibration at lower sys_clk_freq (tested down to 50MHz).
This commit is contained in:
Florent Kermarrec 2021-09-14 16:32:31 +02:00
parent 6a82042fee
commit 6f323f6a7a
1 changed files with 4 additions and 0 deletions
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litedram/phy/s7ddrphy.py
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@ -117,6 +117,10 @@ class S7DDRPHY(Module, AutoCSR):
wdly_dq_bitslip = cdc(self._wdly_dq_bitslip.re) wdly_dq_bitslip = cdc(self._wdly_dq_bitslip.re)
# PHY settings ----------------------------------------------------------------------------- # PHY settings -----------------------------------------------------------------------------
if not with_odelay:
# Write leveling is not possible on Artix7 due to the lack of ODELAYE2, adding +1 to cl
# in MR register increases sys_clk_freq range.
cl += 1
self.settings = PhySettings( self.settings = PhySettings(
phytype = phytype, phytype = phytype,
memtype = memtype, memtype = memtype,