phy/s7ddrphy: Add +1 to CL in MR register to increase sys_clk_freq range.
Allow successful DDR3 calibration at lower sys_clk_freq (tested down to 50MHz).
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@ -117,6 +117,10 @@ class S7DDRPHY(Module, AutoCSR):
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wdly_dq_bitslip = cdc(self._wdly_dq_bitslip.re)
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wdly_dq_bitslip = cdc(self._wdly_dq_bitslip.re)
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# PHY settings -----------------------------------------------------------------------------
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# PHY settings -----------------------------------------------------------------------------
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if not with_odelay:
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# Write leveling is not possible on Artix7 due to the lack of ODELAYE2, adding +1 to cl
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# in MR register increases sys_clk_freq range.
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cl += 1
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self.settings = PhySettings(
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self.settings = PhySettings(
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phytype = phytype,
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phytype = phytype,
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memtype = memtype,
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memtype = memtype,
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