modules: split DDR3 in 2 categories: Chips and SO-DIMMs

This commit is contained in:
Florent Kermarrec 2018-10-01 12:17:50 +02:00
parent 0f46dc4ab7
commit 70620689a0
1 changed files with 28 additions and 27 deletions

View File

@ -235,7 +235,7 @@ class P3R1GE4JGF(SDRAMModule):
tRFC = 127.5
# DDR3
# DDR3 (Chips)
class MT41J128M16(SDRAMModule):
memtype = "DDR3"
# geometry
@ -309,6 +309,33 @@ class MT41K256M16(MT41J256M16):
pass
class K4B2G1646FBCK0(SDRAMModule): ### TODO: optimize and revalidate all timings, at cold and hot temperatures
memtype = "DDR3"
# geometry
nbanks = 8
nrows = 16384
ncols = 1024
# speedgrade invariant timings
tREFI = 7800 # 3900 refresh more often at 85C+
tWTR = (14, 35)
tCCD = (4, None)
tRRD = 10 # 4 * clk = 10ns
# speedgrade related timings
# DDR3-1600
tRP_1600 = 13.125
tRCD_1600 = 13.125
tWR_1600 = 35 # this is hard-coded in MR0 to be 14 cycles, 14 * 2.5 = 35, see sdram_init.py@L224
tRFC_1600 = 160
tFAW_1600 = (None, 40)
# API retro-compatibility
tRP = tRP_1600
tRCD = tRCD_1600
tWR = tWR_1600
tRFC = tRFC_1600
tFAW = tFAW_1600
# DDR3 (SO-DIMM)
class MT8JTF12864(SDRAMModule):
memtype = "DDR3"
# geometry
@ -374,29 +401,3 @@ class MT18KSF1G72HZ(SDRAMModule):
tWR = tWR_1600
tRFC = tRFC_1600
tFAW = tFAW_1600
class K4B2G1646FBCK0(SDRAMModule): ### TODO: optimize and revalidate all timings, at cold and hot temperatures
memtype = "DDR3"
# geometry
nbanks = 8
nrows = 16384
ncols = 1024
# speedgrade invariant timings
tREFI = 7800 # 3900 refresh more often at 85C+
tWTR = (14, 35)
tCCD = (4, None)
tRRD = 10 # 4 * clk = 10ns
# speedgrade related timings
# DDR3-1600
tRP_1600 = 13.125
tRCD_1600 = 13.125
tWR_1600 = 35 # this is hard-coded in MR0 to be 14 cycles, 14 * 2.5 = 35, see sdram_init.py@L224
tRFC_1600 = 160
tFAW_1600 = (None, 40)
# API retro-compatibility
tRP = tRP_1600
tRCD = tRCD_1600
tWR = tWR_1600
tRFC = tRFC_1600
tFAW = tFAW_1600