phy/usddrphy: reorder primitives parameters/signals
This commit is contained in:
Florent Kermarrec
parent
11293dcccc
commit
74f72f91a0
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@ -98,13 +98,14 @@ class USDDRPHY(Module, AutoCSR):
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Instance("OSERDESE3",
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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p_IS_CLK_INVERTED = 0,
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p_IS_CLKDIV_INVERTED = 0,
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p_IS_RST_INVERTED = 0,
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o_OQ = clk_o_nodelay,
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i_RST = ResetSignal(),
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i_CLK = ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
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i_D = 0b10101010
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i_RST = ResetSignal(),
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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i_D = 0b10101010,
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o_OQ = clk_o_nodelay,
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),
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Instance("ODELAYE3",
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p_CASCADE = "NONE",
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@ -113,18 +114,18 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_FORMAT = "TIME",
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_CLK = ClockSignal(),
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i_INC = 1,
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i_EN_VTC = self._en_vtc.storage,
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i_RST = self._cdly_rst.re,
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i_CLK = ClockSignal(),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._cdly_inc.re,
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i_INC = 1,
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i_ODATAIN = clk_o_nodelay,
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o_DATAOUT = clk_o_delayed
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o_DATAOUT = clk_o_delayed,
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),
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Instance("OBUFDS",
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i_I = clk_o_delayed,
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o_O = pads.clk_p,
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o_OB = pads.clk_n
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o_OB = pads.clk_n,
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)
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]
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@ -135,17 +136,17 @@ class USDDRPHY(Module, AutoCSR):
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Instance("OSERDESE3",
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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p_IS_CLK_INVERTED = 0,
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p_IS_CLKDIV_INVERTED = 0,
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p_IS_RST_INVERTED = 0,
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o_OQ = a_o_nodelay,
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i_RST = ResetSignal(),
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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i_D = Cat(dfi.phases[0].address[i], dfi.phases[0].address[i],
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dfi.phases[1].address[i], dfi.phases[1].address[i],
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dfi.phases[2].address[i], dfi.phases[2].address[i],
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dfi.phases[3].address[i], dfi.phases[3].address[i])
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dfi.phases[3].address[i], dfi.phases[3].address[i]),
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o_OQ = a_o_nodelay,
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),
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Instance("ODELAYE3",
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p_CASCADE = "NONE",
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@ -154,13 +155,13 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_FORMAT = "TIME",
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_CLK = ClockSignal(),
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i_INC = 1,
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i_EN_VTC = self._en_vtc.storage,
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i_RST = self._cdly_rst.re,
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i_CLK = ClockSignal(),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._cdly_inc.re,
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i_INC = 1,
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i_ODATAIN = a_o_nodelay,
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o_DATAOUT = pads.a[i]
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o_DATAOUT = pads.a[i],
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)
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]
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@ -176,10 +177,9 @@ class USDDRPHY(Module, AutoCSR):
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Instance("OSERDESE3",
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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p_IS_CLK_INVERTED = 0,
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p_IS_CLKDIV_INVERTED = 0,
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p_IS_RST_INVERTED = 0,
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o_OQ = ba_o_nodelay,
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i_RST = ResetSignal(),
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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@ -187,7 +187,8 @@ class USDDRPHY(Module, AutoCSR):
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dfi.phases[0].bank[i], dfi.phases[0].bank[i],
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dfi.phases[1].bank[i], dfi.phases[1].bank[i],
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dfi.phases[2].bank[i], dfi.phases[2].bank[i],
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dfi.phases[3].bank[i], dfi.phases[3].bank[i])
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dfi.phases[3].bank[i], dfi.phases[3].bank[i]),
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o_OQ = ba_o_nodelay,
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),
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Instance("ODELAYE3",
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p_CASCADE = "NONE",
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@ -196,13 +197,13 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_FORMAT = "TIME",
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_CLK = ClockSignal(),
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i_INC = 1,
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i_EN_VTC = self._en_vtc.storage,
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i_RST = self._cdly_rst.re,
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i_CLK = ClockSignal(),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._cdly_inc.re,
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i_INC = 1,
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i_ODATAIN = ba_o_nodelay,
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o_DATAOUT = pads_ba[i]
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o_DATAOUT = pads_ba[i],
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)
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]
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@ -219,10 +220,9 @@ class USDDRPHY(Module, AutoCSR):
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Instance("OSERDESE3",
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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p_IS_CLK_INVERTED = 0,
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p_IS_CLKDIV_INVERTED = 0,
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p_IS_RST_INVERTED = 0,
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o_OQ = x_o_nodelay,
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i_RST = ResetSignal(),
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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@ -230,7 +230,8 @@ class USDDRPHY(Module, AutoCSR):
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getattr(dfi.phases[0], name), getattr(dfi.phases[0], name),
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getattr(dfi.phases[1], name), getattr(dfi.phases[1], name),
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getattr(dfi.phases[2], name), getattr(dfi.phases[2], name),
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getattr(dfi.phases[3], name), getattr(dfi.phases[3], name))
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getattr(dfi.phases[3], name), getattr(dfi.phases[3], name)),
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o_OQ = x_o_nodelay,
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),
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Instance("ODELAYE3",
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p_CASCADE = "NONE",
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@ -239,13 +240,13 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_FORMAT = "TIME",
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_CLK = ClockSignal(),
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i_INC = 1,
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i_EN_VTC = self._en_vtc.storage,
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i_RST = self._cdly_rst.re,
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i_CLK = ClockSignal(),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._cdly_inc.re,
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i_INC = 1,
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i_ODATAIN = x_o_nodelay,
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o_DATAOUT = getattr(pads, name)
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o_DATAOUT = getattr(pads, name),
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)
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]
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@ -267,10 +268,9 @@ class USDDRPHY(Module, AutoCSR):
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Instance("OSERDESE3",
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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p_IS_CLK_INVERTED = 0,
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p_IS_CLKDIV_INVERTED = 0,
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p_IS_RST_INVERTED = 0,
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o_OQ = dm_o_nodelay,
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i_RST = ResetSignal(),
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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@ -278,7 +278,8 @@ class USDDRPHY(Module, AutoCSR):
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dfi.phases[0].wrdata_mask[i], dfi.phases[0].wrdata_mask[databits//8+i],
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dfi.phases[1].wrdata_mask[i], dfi.phases[1].wrdata_mask[databits//8+i],
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dfi.phases[2].wrdata_mask[i], dfi.phases[2].wrdata_mask[databits//8+i],
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dfi.phases[3].wrdata_mask[i], dfi.phases[3].wrdata_mask[databits//8+i])
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dfi.phases[3].wrdata_mask[i], dfi.phases[3].wrdata_mask[databits//8+i]),
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o_OQ = dm_o_nodelay,
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),
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Instance("ODELAYE3",
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p_CASCADE = "NONE",
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@ -289,13 +290,13 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_FORMAT = "TIME",
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_CLK = ClockSignal(),
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i_INC = 1,
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i_EN_VTC = self._en_vtc.storage,
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i_RST = self._dly_sel.storage[i] & self._wdly_dq_rst.re,
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i_EN_VTC = self._en_vtc.storage,
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i_CLK = ClockSignal(),
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i_CE = self._dly_sel.storage[i] & self._wdly_dq_inc.re,
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i_INC = 1,
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i_ODATAIN = dm_o_nodelay,
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o_DATAOUT = pads.dm[i]
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o_DATAOUT = pads.dm[i],
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)
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]
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@ -318,11 +319,9 @@ class USDDRPHY(Module, AutoCSR):
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Instance("OSERDESE3",
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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p_IS_CLK_INVERTED = 0,
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p_IS_CLKDIV_INVERTED = 0,
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p_IS_RST_INVERTED = 0,
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o_OQ = dqs_nodelay,
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o_T_OUT = dqs_t,
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i_RST = ResetSignal(),
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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@ -332,6 +331,8 @@ class USDDRPHY(Module, AutoCSR):
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dqs_serdes_pattern[2], dqs_serdes_pattern[3],
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dqs_serdes_pattern[4], dqs_serdes_pattern[5],
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dqs_serdes_pattern[6], dqs_serdes_pattern[7]),
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o_OQ = dqs_nodelay,
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o_T_OUT = dqs_t,
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),
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Instance("ODELAYE3",
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@ -343,20 +344,20 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_FORMAT = "TIME",
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = int(tck*1e12/4),
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i_CLK = ClockSignal(),
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i_INC = 1,
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i_EN_VTC = self._en_vtc.storage,
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i_RST = self._dly_sel.storage[i] & self._wdly_dqs_rst.re,
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i_CLK = ClockSignal(),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._dly_sel.storage[i] & self._wdly_dqs_inc.re,
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i_INC = 1,
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o_CNTVALUEOUT = Signal(9) if i != 0 else dqs_taps,
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i_ODATAIN = dqs_nodelay,
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o_DATAOUT = dqs_delayed
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o_DATAOUT = dqs_delayed,
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),
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Instance("IOBUFDSE3",
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i_I = dqs_delayed,
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i_T = dqs_t,
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io_IO = pads.dqs_p[i],
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io_IOB = pads.dqs_n[i]
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io_IOB = pads.dqs_n[i],
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)
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]
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@ -382,11 +383,9 @@ class USDDRPHY(Module, AutoCSR):
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Instance("OSERDESE3",
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p_DATA_WIDTH = 8,
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p_INIT = 0,
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p_IS_RST_INVERTED = 0,
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p_IS_CLK_INVERTED = 0,
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p_IS_CLKDIV_INVERTED = 0,
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p_IS_RST_INVERTED = 0,
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o_OQ = dq_o_nodelay,
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o_T_OUT = dq_t,
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i_RST = ResetSignal(),
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i_CLK = ClockSignal("sys4x"),
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i_CLKDIV = ClockSignal(),
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@ -395,19 +394,21 @@ class USDDRPHY(Module, AutoCSR):
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dfi.phases[1].wrdata[i], dfi.phases[1].wrdata[databits+i],
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dfi.phases[2].wrdata[i], dfi.phases[2].wrdata[databits+i],
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dfi.phases[3].wrdata[i], dfi.phases[3].wrdata[databits+i]),
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i_T = ~oe_dq
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i_T = ~oe_dq,
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o_OQ = dq_o_nodelay,
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o_T_OUT = dq_t,
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),
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Instance("ISERDESE3",
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p_IS_CLK_INVERTED = 0,
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p_IS_CLK_B_INVERTED = 1,
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p_DATA_WIDTH = 8,
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i_D = dq_i_delayed,
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i_RST = ResetSignal(),
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i_FIFO_RD_EN = 0,
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i_CLK = ClockSignal("sys4x"),
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i_CLK_B = ClockSignal("sys4x"), # locally inverted
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i_CLKDIV = ClockSignal(),
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o_Q = dq_bitslip.i
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i_D = dq_i_delayed,
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i_FIFO_RD_EN = 0,
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o_Q = dq_bitslip.i,
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),
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Instance("ODELAYE3",
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p_CASCADE = "NONE",
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@ -418,13 +419,13 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_FORMAT = "TIME",
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_CLK = ClockSignal(),
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i_INC = 1,
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i_EN_VTC = self._en_vtc.storage,
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i_RST = self._dly_sel.storage[i//8] & self._wdly_dq_rst.re,
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i_CLK = ClockSignal(),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._dly_sel.storage[i//8] & self._wdly_dq_inc.re,
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i_INC = 1,
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i_ODATAIN = dq_o_nodelay,
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o_DATAOUT = dq_o_delayed
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o_DATAOUT = dq_o_delayed,
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),
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Instance("IDELAYE3",
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p_CASCADE = "NONE",
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@ -436,19 +437,19 @@ class USDDRPHY(Module, AutoCSR):
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p_DELAY_SRC = "IDATAIN",
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p_DELAY_TYPE = "VARIABLE",
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p_DELAY_VALUE = 0,
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i_CLK = ClockSignal(),
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i_INC = 1,
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i_EN_VTC = self._en_vtc.storage,
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i_RST = self._dly_sel.storage[i//8] & self._rdly_dq_rst.re,
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i_CLK = ClockSignal(),
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i_EN_VTC = self._en_vtc.storage,
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i_CE = self._dly_sel.storage[i//8] & self._rdly_dq_inc.re,
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i_INC = 1,
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i_IDATAIN = dq_i_nodelay,
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o_DATAOUT = dq_i_delayed
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o_DATAOUT = dq_i_delayed,
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),
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Instance("IOBUF",
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i_I = dq_o_delayed,
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o_O = dq_i_nodelay,
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i_T = dq_t,
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io_IO = pads.dq[i]
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io_IO = pads.dq[i],
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)
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]
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self.comb += [
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