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phys: use dfi instead if self.dfi internally

This commit is contained in:
Florent Kermarrec 2019-09-11 09:00:36 +02:00
parent 59c1289432
commit 783258c97f
3 changed files with 75 additions and 75 deletions
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56
litedram/phy/ecp5ddrphy.py
View File

@ -131,7 +131,7 @@ class ECP5DDRPHY(Module, AutoCSR):
)
# DFI Interface ----------------------------------------------------------------------------
self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4)
self.dfi = dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4)
# # #
@ -157,10 +157,10 @@ class ECP5DDRPHY(Module, AutoCSR):
for i in range(addressbits):
self.specials += \
Instance("ODDRX2F",
i_D0=self.dfi.phases[0].address[i],
i_D1=self.dfi.phases[0].address[i],
i_D2=self.dfi.phases[1].address[i],
i_D3=self.dfi.phases[1].address[i],
i_D0=dfi.phases[0].address[i],
i_D1=dfi.phases[0].address[i],
i_D2=dfi.phases[1].address[i],
i_D3=dfi.phases[1].address[i],
i_ECLK=ClockSignal("sys2x"),
i_SCLK=ClockSignal(),
i_RST=ResetSignal("sys2x"),
@ -169,10 +169,10 @@ class ECP5DDRPHY(Module, AutoCSR):
for i in range(bankbits):
self.specials += \
Instance("ODDRX2F",
i_D0=self.dfi.phases[0].bank[i],
i_D1=self.dfi.phases[0].bank[i],
i_D2=self.dfi.phases[1].bank[i],
i_D3=self.dfi.phases[1].bank[i],
i_D0=dfi.phases[0].bank[i],
i_D1=dfi.phases[0].bank[i],
i_D2=dfi.phases[1].bank[i],
i_D3=dfi.phases[1].bank[i],
i_ECLK=ClockSignal("sys2x"),
i_SCLK=ClockSignal(),
i_RST=ResetSignal("sys2x"),
@ -187,10 +187,10 @@ class ECP5DDRPHY(Module, AutoCSR):
for i in range(len(getattr(pads, name))):
self.specials += \
Instance("ODDRX2F",
i_D0=getattr(self.dfi.phases[0], name)[i],
i_D1=getattr(self.dfi.phases[0], name)[i],
i_D2=getattr(self.dfi.phases[1], name)[i],
i_D3=getattr(self.dfi.phases[1], name)[i],
i_D0=getattr(dfi.phases[0], name)[i],
i_D1=getattr(dfi.phases[0], name)[i],
i_D2=getattr(dfi.phases[1], name)[i],
i_D3=getattr(dfi.phases[1], name)[i],
i_ECLK=ClockSignal("sys2x"),
i_SCLK=ClockSignal(),
i_RST=ResetSignal("sys2x"),
@ -280,10 +280,10 @@ class ECP5DDRPHY(Module, AutoCSR):
dm_o_data_d = Signal(8)
dm_o_data_muxed = Signal(4)
self.comb += dm_o_data.eq(Cat(
self.dfi.phases[0].wrdata_mask[0*databits//8+i], self.dfi.phases[0].wrdata_mask[1*databits//8+i],
self.dfi.phases[0].wrdata_mask[2*databits//8+i], self.dfi.phases[0].wrdata_mask[3*databits//8+i],
self.dfi.phases[1].wrdata_mask[0*databits//8+i], self.dfi.phases[1].wrdata_mask[1*databits//8+i],
self.dfi.phases[1].wrdata_mask[2*databits//8+i], self.dfi.phases[1].wrdata_mask[3*databits//8+i]),
dfi.phases[0].wrdata_mask[0*databits//8+i], dfi.phases[0].wrdata_mask[1*databits//8+i],
dfi.phases[0].wrdata_mask[2*databits//8+i], dfi.phases[0].wrdata_mask[3*databits//8+i],
dfi.phases[1].wrdata_mask[0*databits//8+i], dfi.phases[1].wrdata_mask[1*databits//8+i],
dfi.phases[1].wrdata_mask[2*databits//8+i], dfi.phases[1].wrdata_mask[3*databits//8+i]),
)
self.sync += dm_o_data_d.eq(dm_o_data)
self.sync += \
@ -341,10 +341,10 @@ class ECP5DDRPHY(Module, AutoCSR):
dq_o_data_d = Signal(8)
dq_o_data_muxed = Signal(4)
self.comb += dq_o_data.eq(Cat(
self.dfi.phases[0].wrdata[0*databits+j], self.dfi.phases[0].wrdata[1*databits+j],
self.dfi.phases[0].wrdata[2*databits+j], self.dfi.phases[0].wrdata[3*databits+j],
self.dfi.phases[1].wrdata[0*databits+j], self.dfi.phases[1].wrdata[1*databits+j],
self.dfi.phases[1].wrdata[2*databits+j], self.dfi.phases[1].wrdata[3*databits+j])
dfi.phases[0].wrdata[0*databits+j], dfi.phases[0].wrdata[1*databits+j],
dfi.phases[0].wrdata[2*databits+j], dfi.phases[0].wrdata[3*databits+j],
dfi.phases[1].wrdata[0*databits+j], dfi.phases[1].wrdata[1*databits+j],
dfi.phases[1].wrdata[2*databits+j], dfi.phases[1].wrdata[3*databits+j])
)
self.sync += dq_o_data_d.eq(dq_o_data)
self.sync += \
@ -406,10 +406,10 @@ class ECP5DDRPHY(Module, AutoCSR):
dq_bitslip_o_d = Signal(4)
self.sync += dq_bitslip_o_d.eq(dq_bitslip.o)
self.comb += [
self.dfi.phases[0].rddata[0*databits+j].eq(dq_bitslip_o_d[0]), self.dfi.phases[0].rddata[1*databits+j].eq(dq_bitslip_o_d[1]),
self.dfi.phases[0].rddata[2*databits+j].eq(dq_bitslip_o_d[2]), self.dfi.phases[0].rddata[3*databits+j].eq(dq_bitslip_o_d[3]),
self.dfi.phases[1].rddata[0*databits+j].eq(dq_bitslip.o[0]), self.dfi.phases[1].rddata[1*databits+j].eq(dq_bitslip.o[1]),
self.dfi.phases[1].rddata[2*databits+j].eq(dq_bitslip.o[2]), self.dfi.phases[1].rddata[3*databits+j].eq(dq_bitslip.o[3]),
dfi.phases[0].rddata[0*databits+j].eq(dq_bitslip_o_d[0]), dfi.phases[0].rddata[1*databits+j].eq(dq_bitslip_o_d[1]),
dfi.phases[0].rddata[2*databits+j].eq(dq_bitslip_o_d[2]), dfi.phases[0].rddata[3*databits+j].eq(dq_bitslip_o_d[3]),
dfi.phases[1].rddata[0*databits+j].eq(dq_bitslip.o[0]), dfi.phases[1].rddata[1*databits+j].eq(dq_bitslip.o[1]),
dfi.phases[1].rddata[2*databits+j].eq(dq_bitslip.o[2]), dfi.phases[1].rddata[3*databits+j].eq(dq_bitslip.o[3]),
]
self.specials += \
Instance("TSHX2DQA",
@ -429,7 +429,7 @@ class ECP5DDRPHY(Module, AutoCSR):
# ODDRX2DQA latency
# cl_sys_latency
# IDDRX2DQA latency
rddata_en = self.dfi.phases[self.settings.rdphase].rddata_en
rddata_en = dfi.phases[self.settings.rdphase].rddata_en
rddata_ens = Array([Signal() for i in range(self.settings.read_latency-1)])
for i in range(self.settings.read_latency-1):
n_rddata_en = Signal()
@ -437,11 +437,11 @@ class ECP5DDRPHY(Module, AutoCSR):
self.comb += rddata_ens[i].eq(rddata_en)
rddata_en = n_rddata_en
self.sync += [phase.rddata_valid.eq(rddata_en)
for phase in self.dfi.phases]
for phase in dfi.phases]
self.comb += dqs_read.eq(rddata_ens[cl_sys_latency+1] | rddata_ens[cl_sys_latency+2])
oe = Signal()
last_wrdata_en = Signal(cwl_sys_latency+3)
wrphase = self.dfi.phases[self.settings.wrphase]
wrphase = dfi.phases[self.settings.wrphase]
self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:-1]))
self.comb += oe.eq(
last_wrdata_en[cwl_sys_latency-1] |

36
litedram/phy/s6ddrphy.py
View File

@ -73,7 +73,7 @@ class S6HalfRateDDRPHY(Module):
write_latency=0
)
self.dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases)
self.dfi = dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases)
self.clk4x_wr_strb = Signal()
self.clk4x_rd_strb = Signal()
@ -115,7 +115,7 @@ class S6HalfRateDDRPHY(Module):
# register dfi cmds on half_rate clk
r_dfi = Array(Record(phase_cmd_description(addressbits, bankbits, nranks=nranks)) for i in range(nphases))
for n, phase in enumerate(self.dfi.phases):
for n, phase in enumerate(dfi.phases):
sd_sdram_half += [
r_dfi[n].reset_n.eq(phase.reset_n),
r_dfi[n].odt.eq(phase.odt),
@ -235,7 +235,7 @@ class S6HalfRateDDRPHY(Module):
d_dfi = [Record(phase_wrdata_description(nphases*databits)+phase_rddata_description(nphases*databits))
for i in range(2*nphases)]
for n, phase in enumerate(self.dfi.phases):
for n, phase in enumerate(dfi.phases):
self.comb += [
d_dfi[n].wrdata.eq(phase.wrdata),
d_dfi[n].wrdata_mask.eq(phase.wrdata_mask),
@ -402,7 +402,7 @@ class S6HalfRateDDRPHY(Module):
rddata_sr = Signal(self.settings.read_latency)
sd_sys += rddata_sr.eq(Cat(rddata_sr[1:self.settings.read_latency], rddata_en))
for n, phase in enumerate(self.dfi.phases):
for n, phase in enumerate(dfi.phases):
self.comb += [
phase.rddata.eq(d_dfi[n].rddata),
phase.rddata_valid.eq(rddata_sr[0]),
@ -436,7 +436,7 @@ class S6QuarterRateDDRPHY(Module):
write_latency=2//2
)
self.dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases)
self.dfi = dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases)
self.clk8x_wr_strb = half_rate_phy.clk4x_wr_strb
self.clk8x_rd_strb = half_rate_phy.clk4x_rd_strb
@ -469,14 +469,14 @@ class S6QuarterRateDDRPHY(Module):
dfi_omit = set(["rddata", "rddata_valid", "wrdata_en"])
self.comb += [
If(~phase_sel,
self.dfi.phases[0].connect(half_rate_phy.dfi.phases[0], omit=dfi_omit),
self.dfi.phases[1].connect(half_rate_phy.dfi.phases[1], omit=dfi_omit),
dfi.phases[0].connect(half_rate_phy.dfi.phases[0], omit=dfi_omit),
dfi.phases[1].connect(half_rate_phy.dfi.phases[1], omit=dfi_omit),
).Else(
self.dfi.phases[2].connect(half_rate_phy.dfi.phases[0], omit=dfi_omit),
self.dfi.phases[3].connect(half_rate_phy.dfi.phases[1], omit=dfi_omit),
dfi.phases[2].connect(half_rate_phy.dfi.phases[0], omit=dfi_omit),
dfi.phases[3].connect(half_rate_phy.dfi.phases[1], omit=dfi_omit),
),
]
wr_data_en = self.dfi.phases[self.settings.wrphase].wrdata_en & ~phase_sel
wr_data_en = dfi.phases[self.settings.wrphase].wrdata_en & ~phase_sel
wr_data_en_d = Signal()
sd_sys2x += wr_data_en_d.eq(wr_data_en)
self.comb += half_rate_phy.dfi.phases[half_rate_phy.settings.wrphase].wrdata_en.eq(wr_data_en | wr_data_en_d)
@ -492,12 +492,12 @@ class S6QuarterRateDDRPHY(Module):
]
sd_sys += [
self.dfi.phases[0].rddata.eq(rddata[0]),
self.dfi.phases[0].rddata_valid.eq(rddata_valid[0]),
self.dfi.phases[1].rddata.eq(rddata[1]),
self.dfi.phases[1].rddata_valid.eq(rddata_valid[1]),
self.dfi.phases[2].rddata.eq(half_rate_phy.dfi.phases[0].rddata),
self.dfi.phases[2].rddata_valid.eq(half_rate_phy.dfi.phases[0].rddata_valid),
self.dfi.phases[3].rddata.eq(half_rate_phy.dfi.phases[1].rddata),
self.dfi.phases[3].rddata_valid.eq(half_rate_phy.dfi.phases[1].rddata_valid)
dfi.phases[0].rddata.eq(rddata[0]),
dfi.phases[0].rddata_valid.eq(rddata_valid[0]),
dfi.phases[1].rddata.eq(rddata[1]),
dfi.phases[1].rddata_valid.eq(rddata_valid[1]),
dfi.phases[2].rddata.eq(half_rate_phy.dfi.phases[0].rddata),
dfi.phases[2].rddata_valid.eq(half_rate_phy.dfi.phases[0].rddata_valid),
dfi.phases[3].rddata.eq(half_rate_phy.dfi.phases[1].rddata),
dfi.phases[3].rddata_valid.eq(half_rate_phy.dfi.phases[1].rddata_valid)
]

58
litedram/phy/s7ddrphy.py
View File

@ -80,7 +80,7 @@ class S7DDRPHY(Module, AutoCSR):
write_latency=cwl_sys_latency
)
self.dfi = Interface(addressbits, bankbits, nranks, 2*databits, 4)
self.dfi = dfi = Interface(addressbits, bankbits, nranks, 2*databits, 4)
# # #
@ -136,10 +136,10 @@ class S7DDRPHY(Module, AutoCSR):
i_OCE=1,
i_RST=ResetSignal(),
i_CLK=ClockSignal(ddr_clk), i_CLKDIV=ClockSignal(),
i_D1=self.dfi.phases[0].address[i], i_D2=self.dfi.phases[0].address[i],
i_D3=self.dfi.phases[1].address[i], i_D4=self.dfi.phases[1].address[i],
i_D5=self.dfi.phases[2].address[i], i_D6=self.dfi.phases[2].address[i],
i_D7=self.dfi.phases[3].address[i], i_D8=self.dfi.phases[3].address[i]
i_D1=dfi.phases[0].address[i], i_D2=dfi.phases[0].address[i],
i_D3=dfi.phases[1].address[i], i_D4=dfi.phases[1].address[i],
i_D5=dfi.phases[2].address[i], i_D6=dfi.phases[2].address[i],
i_D7=dfi.phases[3].address[i], i_D8=dfi.phases[3].address[i]
)
if with_odelay:
self.specials += \
@ -167,10 +167,10 @@ class S7DDRPHY(Module, AutoCSR):
i_OCE=1,
i_RST=ResetSignal(),
i_CLK=ClockSignal(ddr_clk), i_CLKDIV=ClockSignal(),
i_D1=self.dfi.phases[0].bank[i], i_D2=self.dfi.phases[0].bank[i],
i_D3=self.dfi.phases[1].bank[i], i_D4=self.dfi.phases[1].bank[i],
i_D5=self.dfi.phases[2].bank[i], i_D6=self.dfi.phases[2].bank[i],
i_D7=self.dfi.phases[3].bank[i], i_D8=self.dfi.phases[3].bank[i]
i_D1=dfi.phases[0].bank[i], i_D2=dfi.phases[0].bank[i],
i_D3=dfi.phases[1].bank[i], i_D4=dfi.phases[1].bank[i],
i_D5=dfi.phases[2].bank[i], i_D6=dfi.phases[2].bank[i],
i_D7=dfi.phases[3].bank[i], i_D8=dfi.phases[3].bank[i]
)
if with_odelay:
self.specials += \
@ -204,10 +204,10 @@ class S7DDRPHY(Module, AutoCSR):
i_OCE=1,
i_RST=ResetSignal(),
i_CLK=ClockSignal(ddr_clk), i_CLKDIV=ClockSignal(),
i_D1=getattr(self.dfi.phases[0], name)[i], i_D2=getattr(self.dfi.phases[0], name)[i],
i_D3=getattr(self.dfi.phases[1], name)[i], i_D4=getattr(self.dfi.phases[1], name)[i],
i_D5=getattr(self.dfi.phases[2], name)[i], i_D6=getattr(self.dfi.phases[2], name)[i],
i_D7=getattr(self.dfi.phases[3], name)[i], i_D8=getattr(self.dfi.phases[3], name)[i]
i_D1=getattr(dfi.phases[0], name)[i], i_D2=getattr(dfi.phases[0], name)[i],
i_D3=getattr(dfi.phases[1], name)[i], i_D4=getattr(dfi.phases[1], name)[i],
i_D5=getattr(dfi.phases[2], name)[i], i_D6=getattr(dfi.phases[2], name)[i],
i_D7=getattr(dfi.phases[3], name)[i], i_D8=getattr(dfi.phases[3], name)[i]
)
if with_odelay:
self.specials += \
@ -263,10 +263,10 @@ class S7DDRPHY(Module, AutoCSR):
i_OCE=1,
i_RST=ResetSignal(),
i_CLK=ClockSignal(ddr_clk), i_CLKDIV=ClockSignal(),
i_D1=self.dfi.phases[0].wrdata_mask[i], i_D2=self.dfi.phases[0].wrdata_mask[databits//8+i],
i_D3=self.dfi.phases[1].wrdata_mask[i], i_D4=self.dfi.phases[1].wrdata_mask[databits//8+i],
i_D5=self.dfi.phases[2].wrdata_mask[i], i_D6=self.dfi.phases[2].wrdata_mask[databits//8+i],
i_D7=self.dfi.phases[3].wrdata_mask[i], i_D8=self.dfi.phases[3].wrdata_mask[databits//8+i]
i_D1=dfi.phases[0].wrdata_mask[i], i_D2=dfi.phases[0].wrdata_mask[databits//8+i],
i_D3=dfi.phases[1].wrdata_mask[i], i_D4=dfi.phases[1].wrdata_mask[databits//8+i],
i_D5=dfi.phases[2].wrdata_mask[i], i_D6=dfi.phases[2].wrdata_mask[databits//8+i],
i_D7=dfi.phases[3].wrdata_mask[i], i_D8=dfi.phases[3].wrdata_mask[databits//8+i]
)
if with_odelay:
self.specials += \
@ -342,10 +342,10 @@ class S7DDRPHY(Module, AutoCSR):
i_OCE=1, i_TCE=1,
i_RST=ResetSignal(),
i_CLK=ClockSignal(ddr_clk), i_CLKDIV=ClockSignal(),
i_D1=self.dfi.phases[0].wrdata[i], i_D2=self.dfi.phases[0].wrdata[databits+i],
i_D3=self.dfi.phases[1].wrdata[i], i_D4=self.dfi.phases[1].wrdata[databits+i],
i_D5=self.dfi.phases[2].wrdata[i], i_D6=self.dfi.phases[2].wrdata[databits+i],
i_D7=self.dfi.phases[3].wrdata[i], i_D8=self.dfi.phases[3].wrdata[databits+i],
i_D1=dfi.phases[0].wrdata[i], i_D2=dfi.phases[0].wrdata[databits+i],
i_D3=dfi.phases[1].wrdata[i], i_D4=dfi.phases[1].wrdata[databits+i],
i_D5=dfi.phases[2].wrdata[i], i_D6=dfi.phases[2].wrdata[databits+i],
i_D7=dfi.phases[3].wrdata[i], i_D8=dfi.phases[3].wrdata[databits+i],
i_T1=~oe_dq
)
dq_i_data = Signal(8)
@ -377,10 +377,10 @@ class S7DDRPHY(Module, AutoCSR):
)
self.submodules += dq_bitslip
self.comb += [
self.dfi.phases[0].rddata[i].eq(dq_bitslip.o[0]), self.dfi.phases[0].rddata[databits+i].eq(dq_bitslip.o[1]),
self.dfi.phases[1].rddata[i].eq(dq_bitslip.o[2]), self.dfi.phases[1].rddata[databits+i].eq(dq_bitslip.o[3]),
self.dfi.phases[2].rddata[i].eq(dq_bitslip.o[4]), self.dfi.phases[2].rddata[databits+i].eq(dq_bitslip.o[5]),
self.dfi.phases[3].rddata[i].eq(dq_bitslip.o[6]), self.dfi.phases[3].rddata[databits+i].eq(dq_bitslip.o[7])
dfi.phases[0].rddata[i].eq(dq_bitslip.o[0]), dfi.phases[0].rddata[databits+i].eq(dq_bitslip.o[1]),
dfi.phases[1].rddata[i].eq(dq_bitslip.o[2]), dfi.phases[1].rddata[databits+i].eq(dq_bitslip.o[3]),
dfi.phases[2].rddata[i].eq(dq_bitslip.o[4]), dfi.phases[2].rddata[databits+i].eq(dq_bitslip.o[5]),
dfi.phases[3].rddata[i].eq(dq_bitslip.o[6]), dfi.phases[3].rddata[databits+i].eq(dq_bitslip.o[7])
]
if with_odelay:
@ -423,21 +423,21 @@ class S7DDRPHY(Module, AutoCSR):
# cl_sys_latency cycles CAS
# 2 cycles through ISERDESE2
# 3 cycles through Bitslip
rddata_en = self.dfi.phases[self.settings.rdphase].rddata_en
rddata_en = dfi.phases[self.settings.rdphase].rddata_en
for i in range(self.settings.read_latency-1):
n_rddata_en = Signal()
self.sync += n_rddata_en.eq(rddata_en)
rddata_en = n_rddata_en
if with_odelay:
self.sync += [phase.rddata_valid.eq(rddata_en | self._wlevel_en.storage)
for phase in self.dfi.phases]
for phase in dfi.phases]
else:
self.sync += [phase.rddata_valid.eq(rddata_en)
for phase in self.dfi.phases]
for phase in dfi.phases]
oe = Signal()
last_wrdata_en = Signal(cwl_sys_latency+2)
wrphase = self.dfi.phases[self.settings.wrphase]
wrphase = dfi.phases[self.settings.wrphase]
self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:-1]))
self.comb += oe.eq(
last_wrdata_en[cwl_sys_latency-1] |