frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1
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parent
000a352079
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79314f9549
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@ -28,12 +28,18 @@ class LiteDRAMWishbone2Native(Module):
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[("data", port_data_width), ("we", port_data_width//8)],
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[("data", port_data_width), ("we", port_data_width//8)],
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)
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)
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self.submodules += wdata_converter
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self.submodules += wdata_converter
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wdata_lock = Signal()
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self.comb += [
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self.comb += [
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wdata_converter.sink.valid.eq(wishbone.cyc & wishbone.stb & wishbone.we),
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wdata_converter.sink.valid.eq(wishbone.cyc & wishbone.stb & wishbone.we & ~wdata_lock),
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wdata_converter.sink.data.eq(wishbone.dat_w),
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wdata_converter.sink.data.eq(wishbone.dat_w),
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wdata_converter.sink.we.eq(wishbone.sel),
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wdata_converter.sink.we.eq(wishbone.sel),
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wdata_converter.source.connect(port.wdata)
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wdata_converter.source.connect(port.wdata)
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]
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]
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self.sync += [
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If(wdata_converter.sink.valid & wdata_converter.sink.ready,
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wdata_lock.eq(1)
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)
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]
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# Read Datapath ----------------------------------------------------------------------------
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# Read Datapath ----------------------------------------------------------------------------
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rdata_converter = stream.StrideConverter(
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rdata_converter = stream.StrideConverter(
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@ -55,6 +61,7 @@ class LiteDRAMWishbone2Native(Module):
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port.cmd.valid.eq(wishbone.cyc & wishbone.stb),
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port.cmd.valid.eq(wishbone.cyc & wishbone.stb),
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port.cmd.we.eq(wishbone.we),
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port.cmd.we.eq(wishbone.we),
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port.cmd.addr.eq(wishbone.adr*ratio + count - adr_offset),
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port.cmd.addr.eq(wishbone.adr*ratio + count - adr_offset),
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port.cmd.last.eq(1),
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If(port.cmd.valid & port.cmd.ready,
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If(port.cmd.valid & port.cmd.ready,
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NextValue(count, count + 1),
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NextValue(count, count + 1),
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If(count == (ratio - 1),
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If(count == (ratio - 1),
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@ -69,6 +76,7 @@ class LiteDRAMWishbone2Native(Module):
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)
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)
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fsm.act("WAIT-WRITE",
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fsm.act("WAIT-WRITE",
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If(wdata_converter.sink.ready,
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If(wdata_converter.sink.ready,
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NextValue(wdata_lock, 0),
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wishbone.ack.eq(1),
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wishbone.ack.eq(1),
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NextState("CMD")
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NextState("CMD")
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)
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)
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