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phy/kusddrphy: fix input bit ordering, working :)

This commit is contained in:
Florent Kermarrec 2017-07-08 18:46:53 +02:00
parent 99fe71d622
commit 7b31005bc4
1 changed files with 8 additions and 10 deletions
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18
litedram/phy/kusddrphy.py
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@ -9,8 +9,6 @@ from litex.soc.interconnect.csr import *
from litedram.common import PhySettings
from litedram.phy.dfi import *
# TODO:
# - test on hardware
class KUSDDRPHY(Module, AutoCSR):
def __init__(self, pads):
@ -265,15 +263,15 @@ class KUSDDRPHY(Module, AutoCSR):
)
]
self.comb += [
self.dfi.phases[0].rddata[i].eq(dq_bitslip.o[7]),
self.dfi.phases[1].rddata[i].eq(dq_bitslip.o[5]),
self.dfi.phases[2].rddata[i].eq(dq_bitslip.o[3]),
self.dfi.phases[3].rddata[i].eq(dq_bitslip.o[1]),
self.dfi.phases[0].rddata[i].eq(dq_bitslip.o[0]),
self.dfi.phases[1].rddata[i].eq(dq_bitslip.o[2]),
self.dfi.phases[2].rddata[i].eq(dq_bitslip.o[4]),
self.dfi.phases[3].rddata[i].eq(dq_bitslip.o[6]),
self.dfi.phases[0].rddata[databits+i].eq(dq_bitslip.o[6]),
self.dfi.phases[1].rddata[databits+i].eq(dq_bitslip.o[4]),
self.dfi.phases[2].rddata[databits+i].eq(dq_bitslip.o[2]),
self.dfi.phases[3].rddata[databits+i].eq(dq_bitslip.o[0]),
self.dfi.phases[0].rddata[databits+i].eq(dq_bitslip.o[1]),
self.dfi.phases[1].rddata[databits+i].eq(dq_bitslip.o[3]),
self.dfi.phases[2].rddata[databits+i].eq(dq_bitslip.o[5]),
self.dfi.phases[3].rddata[databits+i].eq(dq_bitslip.o[7]),
]
# Flow control