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modules.py: Add MT41J256M8 (Passes mem_test on HW @ sys4x=500MHz, vexriscv, marble board)

This commit is contained in:
Vamsi Vytla 2021-03-22 13:55:39 -07:00
parent f17037fdb2
commit 7d522cefc3
1 changed files with 14 additions and 0 deletions
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14
litedram/modules.py
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@ -633,6 +633,20 @@ class MT41K64M16(DDR3Module):
}
speedgrade_timings["default"] = speedgrade_timings["1600"]
class MT41J256M8(DDR3Module):
# geometry
nbanks = 8
nrows = 32768
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6), tZQCS=(64, 80))
speedgrade_timings = {
"800": _SpeedgradeTimings(tRP=13.1, tRCD=13.1, tWR=15, tRFC=(64, None), tFAW=(None, 50), tRAS=37.5),
"1066": _SpeedgradeTimings(tRP=13.1, tRCD=13.1, tWR=15, tRFC=(86, None), tFAW=(None, 50), tRAS=37.5),
"1333": _SpeedgradeTimings(tRP=13.5, tRCD=13.5, tWR=15, tRFC=(107, None), tFAW=(None, 45), tRAS=36),
}
speedgrade_timings["default"] = speedgrade_timings["1333"]
class MT41J128M16(DDR3Module):
# geometry
nbanks = 8