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modules: remove unnecessary memtypes.

This commit is contained in:
Florent Kermarrec 2020-09-01 13:43:09 +02:00
parent 7d0dac78c5
commit 7d9c1de0a4
1 changed files with 1 additions and 8 deletions
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9
litedram/modules.py
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@ -511,8 +511,7 @@ class M12L16161A(SDRModule):
class DDRModule(SDRAMModule): memtype = "DDR" class DDRModule(SDRAMModule): memtype = "DDR"
class DDRRegisteredModule(SDRAMRegisteredModule): memtype = "DDR" class DDRRegisteredModule(SDRAMRegisteredModule): memtype = "DDR"
class MT46V32M16(SDRAMModule): class MT46V32M16(DDRModule):
memtype = "DDR"
# geometry # geometry
nbanks = 4 nbanks = 4
nrows = 8192 nrows = 8192
@ -550,7 +549,6 @@ class DDR2Module(SDRAMModule): memtype = "DDR2"
class DDR2RegisteredModule(SDRAMRegisteredModule): memtype = "DDR2" class DDR2RegisteredModule(SDRAMRegisteredModule): memtype = "DDR2"
class MT47H128M8(DDR2Module): class MT47H128M8(DDR2Module):
memtype = "DDR2"
# geometry # geometry
nbanks = 8 nbanks = 8
nrows = 16384 nrows = 16384
@ -560,7 +558,6 @@ class MT47H128M8(DDR2Module):
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)} speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)}
class MT47H32M16(DDR2Module): class MT47H32M16(DDR2Module):
memtype = "DDR2"
# geometry # geometry
nbanks = 4 nbanks = 4
nrows = 8192 nrows = 8192
@ -570,7 +567,6 @@ class MT47H32M16(DDR2Module):
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)} speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)}
class MT47H64M16(DDR2Module): class MT47H64M16(DDR2Module):
memtype = "DDR2"
# geometry # geometry
nbanks = 8 nbanks = 8
nrows = 8192 nrows = 8192
@ -580,7 +576,6 @@ class MT47H64M16(DDR2Module):
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)} speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)}
class P3R1GE4JGF(DDR2Module): class P3R1GE4JGF(DDR2Module):
memtype = "DDR2"
# geometry # geometry
nbanks = 8 nbanks = 8
nrows = 8192 nrows = 8192
@ -595,7 +590,6 @@ class DDR3Module(SDRAMModule): memtype = "DDR3"
class DDR3RegisteredModule(SDRAMRegisteredModule): memtype = "DDR3" class DDR3RegisteredModule(SDRAMRegisteredModule): memtype = "DDR3"
class MT41K64M16(DDR3Module): class MT41K64M16(DDR3Module):
memtype = "DDR3"
# geometry # geometry
nbanks = 8 nbanks = 8
nrows = 8192 nrows = 8192
@ -611,7 +605,6 @@ class MT41K64M16(DDR3Module):
speedgrade_timings["default"] = speedgrade_timings["1600"] speedgrade_timings["default"] = speedgrade_timings["1600"]
class MT41J128M16(DDR3Module): class MT41J128M16(DDR3Module):
memtype = "DDR3"
# geometry # geometry
nbanks = 8 nbanks = 8
nrows = 16384 nrows = 16384