bench: use 115200bauds UART on all targets (fast enough and simplify switch betwen targets).
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@ -86,7 +86,7 @@ class BenchSoC(SoCCore):
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# UARTBone ---------------------------------------------------------------------------------
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# UARTBone ---------------------------------------------------------------------------------
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart")
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
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# Leds -------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.led import LedChaser
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@ -108,7 +108,7 @@ class BenchController:
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# Bench Test ---------------------------------------------------------------------------------------
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# Bench Test ---------------------------------------------------------------------------------------
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def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=10):
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def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=40):
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import time
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import time
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from litex import RemoteClient
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from litex import RemoteClient
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@ -119,7 +119,7 @@ def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t
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# Load BIOS and reboot SoC
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# Load BIOS and reboot SoC
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ctrl = BenchController(bus)
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ctrl = BenchController(bus)
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ctrl.load_rom(bios_filename)
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ctrl.load_rom(bios_filename, delay=1e-4) # FIXME: delay needed @ 115200bauds.
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ctrl.reboot()
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ctrl.reboot()
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# PLL/ClkReg
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# PLL/ClkReg
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@ -185,7 +185,7 @@ def us_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t
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# Load BIOS and reboot SoC
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# Load BIOS and reboot SoC
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ctrl = BenchController(bus)
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ctrl = BenchController(bus)
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ctrl.load_rom(bios_filename, delay=1e-4) # FIXME: delay needed on KCU105 @ 11200bauds.
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ctrl.load_rom(bios_filename, delay=1e-4) # FIXME: delay needed @ 115200bauds.
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ctrl.reboot()
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ctrl.reboot()
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# PLL/ClkReg
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# PLL/ClkReg
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@ -84,7 +84,7 @@ class BenchSoC(SoCCore):
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# UARTBone ---------------------------------------------------------------------------------
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# UARTBone ---------------------------------------------------------------------------------
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart")
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
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# Leds -------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.led import LedChaser
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@ -84,7 +84,7 @@ class BenchSoC(SoCCore):
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# UARTBone ---------------------------------------------------------------------------------
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# UARTBone ---------------------------------------------------------------------------------
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=500e3, cd="uart")
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
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# Leds -------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.led import LedChaser
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