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bench: use 115200bauds UART on all targets (fast enough and simplify switch betwen targets).

This commit is contained in:
Florent Kermarrec 2020-09-14 10:05:55 +02:00
parent e56f74e08b
commit 7eeea34c4e
4 changed files with 6 additions and 6 deletions
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2
bench/arty.py
View File

@ -86,7 +86,7 @@ class BenchSoC(SoCCore):
)
# UARTBone ---------------------------------------------------------------------------------
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart")
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser

6
bench/common.py
View File

@ -108,7 +108,7 @@ class BenchController:
# Bench Test ---------------------------------------------------------------------------------------
def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=10):
def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=40):
import time
from litex import RemoteClient
@ -119,7 +119,7 @@ def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t
# Load BIOS and reboot SoC
ctrl = BenchController(bus)
ctrl.load_rom(bios_filename)
ctrl.load_rom(bios_filename, delay=1e-4) # FIXME: delay needed @ 115200bauds.
ctrl.reboot()
# PLL/ClkReg
@ -185,7 +185,7 @@ def us_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t
# Load BIOS and reboot SoC
ctrl = BenchController(bus)
ctrl.load_rom(bios_filename, delay=1e-4) # FIXME: delay needed on KCU105 @ 11200bauds.
ctrl.load_rom(bios_filename, delay=1e-4) # FIXME: delay needed @ 115200bauds.
ctrl.reboot()
# PLL/ClkReg

2
bench/genesys2.py
View File

@ -84,7 +84,7 @@ class BenchSoC(SoCCore):
)
# UARTBone ---------------------------------------------------------------------------------
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart")
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser

2
bench/kc705.py
View File

@ -84,7 +84,7 @@ class BenchSoC(SoCCore):
)
# UARTBone ---------------------------------------------------------------------------------
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=500e3, cd="uart")
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser