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phy/lpddr5/sim: handle data masking during masked-write

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Jędrzej Boczar 2021-07-13 12:34:22 +02:00 committed by Alessandro Comodi
parent 26cbb700bc
commit 7f742c7fde
1 changed files with 5 additions and 1 deletions
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6
litedram/phy/lpddr5/sim.py
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@ -641,7 +641,11 @@ class BurstHalf(Module):
) )
) )
fsm.act("BURST-WRITE", fsm.act("BURST-WRITE",
ports[cmd_d.bank].we.eq(2**len(ports[cmd_d.bank].we) - 1), If(cmd_d.masked,
ports[cmd_d.bank].we.eq(~pads.dmi), # DMI HIGH masks a byte
).Else(
ports[cmd_d.bank].we.eq(2**len(ports[cmd_d.bank].we) - 1),
),
ports[cmd_d.bank].dat_w.eq(pads.dq), ports[cmd_d.bank].dat_w.eq(pads.dq),
self.log.debug("WRITE[%d]: bank=%d, row=%d, col=%d, dq=0x%04x dm=0x%02b", self.log.debug("WRITE[%d]: bank=%d, row=%d, col=%d, dq=0x%04x dm=0x%02b",
burst_beat, cmd_d.bank, cmd_d.row, current_col, pads.dq, pads.dmi, burst_beat, cmd_d.bank, cmd_d.row, current_col, pads.dq, pads.dmi,