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modules: add EDY4016A DDR4

This commit is contained in:
Florent Kermarrec 2018-11-04 18:50:50 +01:00
parent 346e64c3f2
commit 8181fea0da
1 changed files with 16 additions and 0 deletions
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16
litedram/modules.py
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@ -312,3 +312,19 @@ class MT18KSF1G72HZ(SDRAMModule):
"1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=13.125, tRFC=128, tFAW=(None, 40), tRAS=None), "1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=13.125, tRFC=128, tFAW=(None, 40), tRAS=None),
} }
speedgrade_timings["default"] = speedgrade_timings["1600"] speedgrade_timings["default"] = speedgrade_timings["1600"]
# DDR4 (Chips)
class EDY4016A(SDRAMModule):
memtype = "DDR4"
# geometry
nbanks_groups = 2
nbanks = 4
nrows = 32768
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 4.9))
speedgrade_timings = {
"2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=260, tFAW=(28, 30), tRAS=32),
}
speedgrade_timings["default"] = speedgrade_timings["2400"]