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modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns)

This commit is contained in:
Florent Kermarrec 2018-07-06 14:28:52 +02:00
parent f4b92b6142
commit 82b7199770
1 changed files with 4 additions and 4 deletions
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8
litedram/modules.py
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@ -214,7 +214,7 @@ class MT41K128M16(SDRAMModule):
tRP = 13.75 tRP = 13.75
tRCD = 13.75 tRCD = 13.75
tWR = 15 tWR = 15
tWTR = 8 tWTR = 3
tREFI = 64*1000*1000/8192 tREFI = 64*1000*1000/8192
tRFC = 160 tRFC = 160
@ -229,7 +229,7 @@ class MT41K256M16(SDRAMModule):
tRP = 13.75 tRP = 13.75
tRCD = 13.75 tRCD = 13.75
tWR = 15 tWR = 15
tWTR = 8 tWTR = 3
tREFI = 64*1000*1000/8192 tREFI = 64*1000*1000/8192
tRFC = 260 tRFC = 260
@ -244,7 +244,7 @@ class MT41J256M16(SDRAMModule):
tRP = 13.75 tRP = 13.75
tRCD = 13.75 tRCD = 13.75
tWR = 15 tWR = 15
tWTR = 8 tWTR = 3
tREFI = 64*1000*1000/8192 tREFI = 64*1000*1000/8192
tRFC = 260 tRFC = 260
@ -259,6 +259,6 @@ class MT18KSF1G72HZ_1G6(SDRAMModule):
tRP = 13.75 tRP = 13.75
tRCD = 13.75 tRCD = 13.75
tWR = 15 tWR = 15
tWTR = 8 tWTR = 3
tREFI = 64*1000*1000/8192 tREFI = 64*1000*1000/8192
tRFC = 260 tRFC = 260