Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/model: update TODO

This commit is contained in:
Florent Kermarrec 2020-02-13 16:57:47 +01:00
parent 5d9b28aa10
commit 8594e12b3a
1 changed files with 1 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litedram/phy/model.py
View File

@ -4,11 +4,7 @@
# SDRAM simulation PHY at DFI level tested with SDR/DDR/DDR2/LPDDR/DDR3 # SDRAM simulation PHY at DFI level tested with SDR/DDR/DDR2/LPDDR/DDR3
# TODO: # TODO:
# - test/add DDR4 support.
# - add init/dump capabilities.
# - add multirank support. # - add multirank support.
# - add bandwidth/efficiency measurements.
# - add timings checks.
from migen import * from migen import *