phy/model: update TODO

2020-02-13 16:57:47 +01:00 · 2020-02-13 16:57:47 +01:00 · 8594e12b3a
parent 5d9b28aa10
commit 8594e12b3a
1 changed files with 1 additions and 5 deletions
--- a/litedram/phy/model.py
+++ b/litedram/phy/model.py
@ -4,11 +4,7 @@

 # SDRAM simulation PHY at DFI level tested with SDR/DDR/DDR2/LPDDR/DDR3
 # TODO:
-# - test/add DDR4 support.
-# - add init/dump capabilities.
 # - add multirank support.
-# - add bandwidth/efficiency measurements.
-# - add timings checks.

 from migen import *