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Merge pull request #46 from enjoy-digital/WritePrechargeFix 

Update the write-to-precharge timings so it works with 1:2
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enjoy-digital 2018-09-25 20:59:36 +02:00 committed by GitHub
parent 30c32f557c 0405f4156d
commit 869c8ee618
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1 changed files with 3 additions and 1 deletions
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litedram/core/bankmachine.py
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@ -1,3 +1,4 @@
import math
from migen import * from migen import *
from migen.genlib.misc import WaitTimer from migen.genlib.misc import WaitTimer
@ -84,7 +85,8 @@ class BankMachine(Module):
] ]
# Respect write-to-precharge specification # Respect write-to-precharge specification
precharge_time = 2 + settings.timing.tWR - 1 + 1 write_latency = math.ceil(settings.phy.cwl / settings.phy.nphases)
precharge_time = write_latency + settings.timing.tWR - 1 + settings.timing.tCCD
precharge_timer = WaitTimer(precharge_time) precharge_timer = WaitTimer(precharge_time)
self.submodules += precharge_timer self.submodules += precharge_timer
self.comb += precharge_timer.wait.eq(~(cmd.valid & cmd.ready & cmd.is_write)) self.comb += precharge_timer.wait.eq(~(cmd.valid & cmd.ready & cmd.is_write))