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frontend/bist: restrict lfsr to 32 bit allow bist with large ddram 

msbs data are then filled with zeros, but we should fix lfsr generation to avoid this
This commit is contained in:
Florent Kermarrec 2017-07-10 12:02:13 +02:00
parent 33ca8d604e
commit 86b0cc0a56
1 changed files with 2 additions and 2 deletions
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4
litedram/frontend/bist.py
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@ -84,7 +84,7 @@ class _LiteDRAMBISTGenerator(Module):
# # # # # #
gen_cls = LFSR if random else Counter gen_cls = LFSR if random else Counter
gen = gen_cls(dram_port.dw) gen = gen_cls(min(dram_port.dw, 32)) # FIXME: remove lfsr limitation
dma = LiteDRAMDMAWriter(dram_port) dma = LiteDRAMDMAWriter(dram_port)
self.submodules += dma, gen self.submodules += dma, gen
@ -210,7 +210,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
# # # # # #
gen_cls = LFSR if random else Counter gen_cls = LFSR if random else Counter
gen = gen_cls(dram_port.dw) gen = gen_cls(min(dram_port.dw, 32)) # FIXME: remove lfsr limitation
dma = LiteDRAMDMAReader(dram_port) dma = LiteDRAMDMAReader(dram_port)
self.submodules += dma, gen self.submodules += dma, gen