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frontend/adaptation: small optimization on LiteDRAMPortUpConverter (still to be refactored)

This commit is contained in:
Florent Kermarrec 2016-06-12 16:53:44 +02:00
parent edbebfa8a2
commit 870638fc50
1 changed files with 6 additions and 3 deletions
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9
litedram/frontend/adaptation.py
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@ -151,8 +151,9 @@ class LiteDRAMPortUpConverter(Module):
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
counter_reset.eq(1),
port_from.cmd.ready.eq(1),
If(port_from.cmd.valid,
counter_ce.eq(1),
NextValue(we, port_from.cmd.we),
NextValue(address, port_from.cmd.adr),
If(we,
@ -170,7 +171,8 @@ class LiteDRAMPortUpConverter(Module):
If(we,
NextState("GENERATE")
).Else(
NextState("IDLE") # FIXME
NextState("IDLE"), # FIXME
port_from.cmd.ready.eq(1),
)
)
)
@ -181,7 +183,8 @@ class LiteDRAMPortUpConverter(Module):
port_to.cmd.adr.eq(address[log2_int(ratio):]),
If(port_to.cmd.ready,
If(we,
NextState("IDLE")
NextState("IDLE"),
port_from.cmd.ready.eq(1)
).Else(
NextState("RECEIVE") # FIXME
)