frontend/adaptation: add workaround on LiteDRAMPortUpConverter to increase throughput on reads (to be fixed since only working for our actual usecase)
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@ -155,7 +155,11 @@ class LiteDRAMPortUpConverter(Module):
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If(port_from.cmd.valid,
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NextValue(we, port_from.cmd.we),
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NextValue(address, port_from.cmd.adr),
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NextState("RECEIVE")
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If(we,
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NextState("RECEIVE")
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).Else(
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NextState("GENERATE") # FIXME
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)
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)
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)
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fsm.act("RECEIVE",
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@ -163,7 +167,11 @@ class LiteDRAMPortUpConverter(Module):
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If(port_from.cmd.valid,
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counter_ce.eq(1),
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If(counter == ratio-1,
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NextState("GENERATE")
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If(we,
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NextState("GENERATE")
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).Else(
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NextState("IDLE") # FIXME
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)
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)
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)
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)
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@ -172,7 +180,11 @@ class LiteDRAMPortUpConverter(Module):
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port_to.cmd.we.eq(we),
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port_to.cmd.adr.eq(address[log2_int(ratio):]),
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If(port_to.cmd.ready,
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NextState("IDLE")
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If(we,
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NextState("IDLE")
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).Else(
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NextState("RECEIVE") # FIXME
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)
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)
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)
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