frontend/adaptation: add workaround on LiteDRAMPortUpConverter to increase throughput on reads (to be fixed since only working for our actual usecase)

This commit is contained in:
Florent Kermarrec 2016-06-10 22:07:53 +02:00
parent 66907f1468
commit edbebfa8a2
1 changed files with 15 additions and 3 deletions

View File

@ -155,7 +155,11 @@ class LiteDRAMPortUpConverter(Module):
If(port_from.cmd.valid,
NextValue(we, port_from.cmd.we),
NextValue(address, port_from.cmd.adr),
NextState("RECEIVE")
If(we,
NextState("RECEIVE")
).Else(
NextState("GENERATE") # FIXME
)
)
)
fsm.act("RECEIVE",
@ -163,7 +167,11 @@ class LiteDRAMPortUpConverter(Module):
If(port_from.cmd.valid,
counter_ce.eq(1),
If(counter == ratio-1,
NextState("GENERATE")
If(we,
NextState("GENERATE")
).Else(
NextState("IDLE") # FIXME
)
)
)
)
@ -172,7 +180,11 @@ class LiteDRAMPortUpConverter(Module):
port_to.cmd.we.eq(we),
port_to.cmd.adr.eq(address[log2_int(ratio):]),
If(port_to.cmd.ready,
NextState("IDLE")
If(we,
NextState("IDLE")
).Else(
NextState("RECEIVE") # FIXME
)
)
)