frontend/adaptation: small optimization on LiteDRAMPortUpConverter (still to be refactored)
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@ -151,8 +151,9 @@ class LiteDRAMPortUpConverter(Module):
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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fsm.act("IDLE",
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counter_reset.eq(1),
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port_from.cmd.ready.eq(1),
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If(port_from.cmd.valid,
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If(port_from.cmd.valid,
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counter_ce.eq(1),
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NextValue(we, port_from.cmd.we),
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NextValue(we, port_from.cmd.we),
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NextValue(address, port_from.cmd.adr),
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NextValue(address, port_from.cmd.adr),
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If(we,
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If(we,
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@ -170,7 +171,8 @@ class LiteDRAMPortUpConverter(Module):
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If(we,
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If(we,
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NextState("GENERATE")
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NextState("GENERATE")
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).Else(
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).Else(
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NextState("IDLE") # FIXME
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NextState("IDLE"), # FIXME
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port_from.cmd.ready.eq(1),
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)
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)
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)
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)
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)
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)
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@ -181,7 +183,8 @@ class LiteDRAMPortUpConverter(Module):
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port_to.cmd.adr.eq(address[log2_int(ratio):]),
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port_to.cmd.adr.eq(address[log2_int(ratio):]),
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If(port_to.cmd.ready,
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If(port_to.cmd.ready,
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If(we,
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If(we,
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NextState("IDLE")
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NextState("IDLE"),
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port_from.cmd.ready.eq(1)
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).Else(
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).Else(
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NextState("RECEIVE") # FIXME
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NextState("RECEIVE") # FIXME
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)
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)
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