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frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup

This commit is contained in:
Florent Kermarrec 2018-08-09 09:33:24 +02:00
parent 26f3f016e1
commit 873b970fca
2 changed files with 19 additions and 18 deletions
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18
litedram/common.py
View File

@ -1,6 +1,10 @@
from migen import * from migen import *
from litex.soc.interconnect import stream from litex.soc.interconnect import stream
bankbits_max = 3
class PhySettings: class PhySettings:
def __init__(self, memtype, dfi_databits, def __init__(self, memtype, dfi_databits,
nphases, nphases,
@ -56,12 +60,12 @@ def cmd_layout(aw):
] ]
def data_layout(dw, bankbits): def data_layout(dw):
return [ return [
("wdata", dw, DIR_M_TO_S), ("wdata", dw, DIR_M_TO_S),
("wdata_we", dw//8, DIR_M_TO_S), ("wdata_we", dw//8, DIR_M_TO_S),
("rdata", dw, DIR_S_TO_M), ("rdata", dw, DIR_S_TO_M),
("rbank", bankbits, DIR_S_TO_M) ("rbank", bankbits_max, DIR_S_TO_M)
] ]
@ -73,7 +77,7 @@ class LiteDRAMInterface(Record):
self.settings = settings self.settings = settings
layout = [("bank"+str(i), cmd_layout(self.aw)) for i in range(self.nbanks)] layout = [("bank"+str(i), cmd_layout(self.aw)) for i in range(self.nbanks)]
layout += data_layout(self.dw, settings.geom.bankbits) layout += data_layout(self.dw)
Record.__init__(self, layout) Record.__init__(self, layout)
def cmd_description(aw): def cmd_description(aw):
@ -88,12 +92,12 @@ def wdata_description(dw):
("we", dw//8) ("we", dw//8)
] ]
def rdata_description(dw, nbanks): def rdata_description(dw):
return [("data", dw), ("bank", nbanks)] return [("data", dw), ("bank", bankbits_max)]
class LiteDRAMPort: class LiteDRAMPort:
def __init__(self, mode, aw, dw, bankbits, cd="sys", id=0): def __init__(self, mode, aw, dw, cd="sys", id=0):
self.mode = mode self.mode = mode
self.aw = aw self.aw = aw
self.dw = dw self.dw = dw
@ -104,7 +108,7 @@ class LiteDRAMPort:
self.cmd = stream.Endpoint(cmd_description(aw)) self.cmd = stream.Endpoint(cmd_description(aw))
self.wdata = stream.Endpoint(wdata_description(dw)) self.wdata = stream.Endpoint(wdata_description(dw))
self.rdata = stream.Endpoint(rdata_description(dw, bankbits)) self.rdata = stream.Endpoint(rdata_description(dw))
self.flush = Signal() self.flush = Signal()

11
litedram/frontend/crossbar.py
View File

@ -33,12 +33,12 @@ class LiteDRAMCrossbar(Module):
dw = self.dw dw = self.dw
# crossbar port # crossbar port
port = LiteDRAMPort(mode, self.rca_bits + self.bank_bits, self.dw, self.bank_bits, "sys", len(self.masters)) port = LiteDRAMPort(mode, self.rca_bits + self.bank_bits, self.dw, "sys", len(self.masters))
self.masters.append(port) self.masters.append(port)
# clock domain crossing # clock domain crossing
if cd != "sys": if cd != "sys":
new_port = LiteDRAMPort(mode, port.aw, port.dw, self.bank_bits, cd, port.id) new_port = LiteDRAMPort(mode, port.aw, port.dw, cd, port.id)
self.submodules += LiteDRAMPortCDC(new_port, port) self.submodules += LiteDRAMPortCDC(new_port, port)
port = new_port port = new_port
@ -48,7 +48,7 @@ class LiteDRAMCrossbar(Module):
adr_shift = -log2_int(dw//self.dw) adr_shift = -log2_int(dw//self.dw)
else: else:
adr_shift = log2_int(self.dw//dw) adr_shift = log2_int(self.dw//dw)
new_port = LiteDRAMPort(mode, port.aw + adr_shift, dw, self.bank_bits, cd, port.id) new_port = LiteDRAMPort(mode, port.aw + adr_shift, dw, cd, port.id)
self.submodules += ClockDomainsRenamer(cd)(LiteDRAMPortConverter(new_port, port, reverse)) self.submodules += ClockDomainsRenamer(cd)(LiteDRAMPortConverter(new_port, port, reverse))
port = new_port port = new_port
@ -92,10 +92,7 @@ class LiteDRAMCrossbar(Module):
] ]
# Get rdata source bank # Get rdata source bank
self.sync += \ self.sync += If((arbiter.grant == nm) & bank.rdata_valid, rbank.eq(nb))
If((arbiter.grant == nm) & bank.rdata_valid,
rbank.eq(nb)
)
# route requests # route requests
self.comb += [ self.comb += [