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litedram
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common: add id to ports

This commit is contained in:
Florent Kermarrec 2017-06-27 15:06:12 +02:00
parent 9ce2f67bb1
commit 883e97101a
2 changed files with 5 additions and 4 deletions
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3
litedram/common.py
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@ -89,11 +89,12 @@ def rdata_description(dw):
class LiteDRAMPort:
def __init__(self, mode, aw, dw, cd="sys"):
def __init__(self, mode, aw, dw, cd="sys", id=0):
self.mode = mode
self.aw = aw
self.dw = dw
self.cd = cd
self.id = id
self.lock = Signal()

6
litedram/frontend/crossbar.py
View File

@ -33,12 +33,12 @@ class LiteDRAMCrossbar(Module):
dw = self.dw
# crossbar port
port = LiteDRAMPort(mode, self.rca_bits + self.bank_bits, self.dw, "sys")
port = LiteDRAMPort(mode, self.rca_bits + self.bank_bits, self.dw, "sys", len(self.masters))
self.masters.append(port)
# clock domain crossing
if cd != "sys":
new_port = LiteDRAMPort(mode, port.aw, port.dw, cd)
new_port = LiteDRAMPort(mode, port.aw, port.dw, cd, port.id)
self.submodules += LiteDRAMPortCDC(new_port, port)
port = new_port
@ -48,7 +48,7 @@ class LiteDRAMCrossbar(Module):
adr_shift = -log2_int(dw//self.dw)
else:
adr_shift = log2_int(self.dw//dw)
new_port = LiteDRAMPort(mode, port.aw + adr_shift, dw, cd=cd)
new_port = LiteDRAMPort(mode, port.aw + adr_shift, dw, cd, port.id)
self.submodules += ClockDomainsRenamer(cd)(LiteDRAMPortConverter(new_port, port, reverse))
port = new_port