Merge pull request #202 from ozbenh/sim-autoinit
Default to HW control for sim
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commit
899462c864
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@ -49,7 +49,11 @@ class DFIInjector(Module, AutoCSR):
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self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
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self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
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self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
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self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
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self._control = CSRStorage(4) # sel, cke, odt, reset_n
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# sel, cke, odt, reset_n
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#
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# sel defaults 1 (HW control) so sim models don't need to perform
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# the initialization sequence
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self._control = CSRStorage(4, reset=0x01)
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for n, phase in enumerate(inti.phases):
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for n, phase in enumerate(inti.phases):
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setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
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setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
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