common: use cmd/wdata/rdata stream on LiteDRAMPort
This commit is contained in:
Florent Kermarrec
parent
30bacfeb1b
commit
8d066caea9
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@ -1,4 +1,5 @@
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from litex.gen import *
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from litex.soc.interconnect import stream
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class PhySettings:
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def __init__(self, memtype, dfi_databits,
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@ -47,10 +48,8 @@ def cmd_layout(aw):
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("adr", aw, DIR_M_TO_S),
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("lock", 1, DIR_S_TO_M), # only used internally
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("wdata_valid", 1, DIR_M_TO_S),
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("wdata_ready", 1, DIR_S_TO_M),
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("rdata_valid", 1, DIR_S_TO_M),
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("rdata_ready", 1, DIR_M_TO_S)
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("rdata_valid", 1, DIR_S_TO_M)
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]
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@ -73,15 +72,33 @@ class LiteDRAMInterface(Record):
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layout += data_layout(self.dw)
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Record.__init__(self, layout)
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def cmd_description(aw):
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return [
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("we", 1),
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("adr", aw)
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]
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class LiteDRAMPort(Record):
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def wdata_description(dw):
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return [
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("data", dw),
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("we", dw//8)
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]
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def rdata_description(dw):
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return [("data", dw)]
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class LiteDRAMPort:
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def __init__(self, aw, dw, cd):
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self.aw = aw
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self.dw = dw
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self.cd = cd
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layout = cmd_layout(aw) + data_layout(dw)
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Record.__init__(self, layout)
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self.lock = Signal()
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self.cmd = stream.Endpoint(cmd_description(aw))
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self.wdata = stream.Endpoint(wdata_description(dw))
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self.rdata = stream.Endpoint(rdata_description(dw))
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def cmd_request_layout(a, ba):
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@ -14,9 +14,9 @@ class LiteDRAMWishboneBridge(Module):
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)
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)
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fsm.act("REQUEST",
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port.valid.eq(1),
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port.we.eq(wishbone.we),
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If(port.ready,
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port.cmd.valid.eq(1),
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port.cmd.we.eq(wishbone.we),
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If(port.cmd.ready,
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If(wishbone.we,
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NextState("WRITE_DATA")
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).Else(
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@ -25,15 +25,15 @@ class LiteDRAMWishboneBridge(Module):
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)
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)
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fsm.act("WRITE_DATA",
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port.wdata_valid.eq(1),
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If(port.wdata_ready,
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port.wdata.valid.eq(1),
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If(port.wdata.ready,
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wishbone.ack.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("READ_DATA",
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port.rdata_ready.eq(1),
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If(port.rdata_valid,
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port.rdata.ready.eq(1),
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If(port.rdata.valid,
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wishbone.ack.eq(1),
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NextState("IDLE")
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)
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@ -41,8 +41,8 @@ class LiteDRAMWishboneBridge(Module):
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# Address / Datapath
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self.comb += [
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port.adr.eq(wishbone.adr),
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port.wdata_we.eq(wishbone.sel),
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port.wdata.eq(wishbone.dat_w),
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wishbone.dat_r.eq(port.rdata)
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port.cmd.adr.eq(wishbone.adr),
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port.wdata.we.eq(wishbone.sel),
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port.wdata.data.eq(wishbone.dat_w),
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wishbone.dat_r.eq(port.rdata.data)
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]
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@ -21,43 +21,24 @@ class LiteDRAMAsyncAdapter(Module):
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cmd_fifo = ClockDomainsRenamer({"write": cd_from, "read": cd_to})(cmd_fifo)
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self.submodules += cmd_fifo
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self.comb += [
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cmd_fifo.sink.valid.eq(port_from.valid),
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cmd_fifo.sink.we.eq(port_from.we),
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cmd_fifo.sink.adr.eq(port_from.adr),
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port_from.ready.eq(cmd_fifo.sink.ready),
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port_to.valid.eq(cmd_fifo.source.valid),
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port_to.we.eq(cmd_fifo.source.we),
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port_to.adr.eq(cmd_fifo.source.adr),
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cmd_fifo.source.ready.eq(port_to.ready)
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port_from.cmd.connect(cmd_fifo.sink),
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cmd_fifo.source.connect(port_to.cmd)
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]
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wdata_fifo = stream.AsyncFIFO([("data", dw), ("we", dw//8)], 4)
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wdata_fifo = ClockDomainsRenamer({"write": cd_from, "read": cd_to})(wdata_fifo)
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self.submodules += wdata_fifo
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self.comb += [
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wdata_fifo.sink.valid.eq(port_from.wdata_valid),
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wdata_fifo.sink.data.eq(port_from.wdata),
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wdata_fifo.sink.we.eq(port_from.wdata_we),
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port_from.wdata_ready.eq(wdata_fifo.sink.ready),
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port_to.wdata_valid.eq(wdata_fifo.source.valid),
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port_to.wdata.eq(wdata_fifo.source.data),
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port_to.wdata_we.eq(wdata_fifo.source.we),
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wdata_fifo.source.ready.eq(port_to.wdata_ready)
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port_from.wdata.connect(wdata_fifo.sink),
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wdata_fifo.source.connect(port_to.wdata)
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]
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rdata_fifo = stream.AsyncFIFO([("data", dw)], 4)
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rdata_fifo = ClockDomainsRenamer({"write": cd_to, "read": cd_from})(rdata_fifo)
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self.submodules += rdata_fifo
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self.comb += [
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rdata_fifo.sink.valid.eq(port_to.rdata_valid),
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rdata_fifo.sink.data.eq(port_to.rdata),
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port_to.rdata_ready.eq(rdata_fifo.sink.ready),
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port_from.rdata_valid.eq(rdata_fifo.source.valid),
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port_from.rdata.eq(rdata_fifo.source.data),
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rdata_fifo.source.ready.eq(port_from.rdata_ready)
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port_to.rdata.connect(rddata_fifo.sink),
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rddata_fifo.source.connect(port_from.rdata)
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]
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@ -118,7 +99,7 @@ class LiteDRAMCrossbar(Module):
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# arbitrate
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bank_selected = [(ba == nb) & ~locked for ba, locked in zip(m_ba, master_locked)]
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bank_requested = [bs & master.valid for bs, master in zip(bank_selected, self.masters)]
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bank_requested = [bs & master.cmd.valid for bs, master in zip(bank_selected, self.masters)]
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self.comb += [
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arbiter.request.eq(Cat(*bank_requested)),
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arbiter.ce.eq(~bank.valid & ~bank.lock)
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@ -127,7 +108,7 @@ class LiteDRAMCrossbar(Module):
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# route requests
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self.comb += [
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bank.adr.eq(Array(m_rca)[arbiter.grant]),
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bank.we.eq(Array(self.masters)[arbiter.grant].we),
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bank.we.eq(Array(self.masters)[arbiter.grant].cmd.we),
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bank.valid.eq(Array(bank_requested)[arbiter.grant])
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]
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master_readys = [master_ready | ((arbiter.grant == nm) & bank_selected[nm] & bank.ready)
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@ -152,18 +133,18 @@ class LiteDRAMCrossbar(Module):
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master_rdata_valids[nm] = master_rdata_valid
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for master, master_ready in zip(self.masters, master_readys):
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self.comb += master.ready.eq(master_ready)
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self.comb += master.cmd.ready.eq(master_ready)
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for master, master_wdata_ready in zip(self.masters, master_wdata_readys):
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self.comb += master.wdata_ready.eq(master_wdata_ready)
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self.comb += master.wdata.ready.eq(master_wdata_ready)
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for master, master_rdata_valid in zip(self.masters, master_rdata_valids):
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self.comb += master.rdata_valid.eq(master_rdata_valid)
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self.comb += master.rdata.valid.eq(master_rdata_valid)
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# route data writes
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wdata_cases = {}
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for nm, master in enumerate(self.masters):
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wdata_cases[2**nm] = [
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controller.wdata.eq(master.wdata),
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controller.wdata_we.eq(master.wdata_we)
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controller.wdata.eq(master.wdata.data),
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controller.wdata_we.eq(master.wdata.we)
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]
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wdata_cases["default"] = [
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controller.wdata.eq(0),
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@ -173,7 +154,7 @@ class LiteDRAMCrossbar(Module):
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# route data reads
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for master in self.masters:
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self.comb += master.rdata.eq(self.controller.rdata)
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self.comb += master.rdata.data.eq(self.controller.rdata)
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def split_master_addresses(self, bank_bits, rca_bits, cba_shift):
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m_ba = [] # bank address
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@ -182,15 +163,15 @@ class LiteDRAMCrossbar(Module):
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cba = Signal(self.bank_bits)
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rca = Signal(self.rca_bits)
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cba_upper = cba_shift + bank_bits
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self.comb += cba.eq(master.adr[cba_shift:cba_upper])
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self.comb += cba.eq(master.cmd.adr[cba_shift:cba_upper])
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if cba_shift < self.rca_bits:
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if cba_shift:
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self.comb += rca.eq(Cat(master.adr[:cba_shift],
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master.adr[cba_upper:]))
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self.comb += rca.eq(Cat(master.cmd.adr[:cba_shift],
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master.cmd.adr[cba_upper:]))
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else:
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self.comb += rca.eq(master.adr[cba_upper:])
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self.comb += rca.eq(master.cmd.adr[cba_upper:])
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else:
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self.comb += rca.eq(master.adr[:cba_shift])
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self.comb += rca.eq(master.cmd.adr[:cba_shift])
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ba = cba
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@ -15,11 +15,11 @@ class LiteDRAMDMAReader(Module):
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request_issued = Signal()
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self.comb += [
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port.we.eq(0),
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port.valid.eq(sink.valid & request_enable),
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port.adr.eq(sink.address),
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sink.ready.eq(port.ready & request_enable),
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request_issued.eq(port.valid & port.ready)
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port.cmd.we.eq(0),
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port.cmd.valid.eq(sink.valid & request_enable),
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port.cmd.adr.eq(sink.address),
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sink.ready.eq(port.cmd.ready & request_enable),
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request_issued.eq(port.cmd.valid & port.cmd.ready)
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]
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# FIFO reservation level counter
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@ -41,10 +41,7 @@ class LiteDRAMDMAReader(Module):
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self.submodules += fifo
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self.comb += [
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fifo.sink.data.eq(port.rdata),
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fifo.sink.valid.eq(port.rdata_valid),
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port.rdata_ready.eq(fifo.sink.ready),
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port.rdata.connect(fifo.sink),
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fifo.source.connect(source),
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data_dequeued.eq(source.valid & source.ready)
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]
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@ -61,17 +58,17 @@ class LiteDRAMDMAWriter(Module):
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self.submodules += fifo
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self.comb += [
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port.we.eq(1),
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port.valid.eq(fifo.sink.ready & sink.valid),
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port.adr.eq(sink.address),
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sink.ready.eq(fifo.sink.ready & port.ready),
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fifo.sink.valid.eq(sink.valid & port.ready),
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port.cmd.we.eq(1),
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port.cmd.valid.eq(fifo.sink.ready & sink.valid),
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port.cmd.adr.eq(sink.address),
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sink.ready.eq(fifo.sink.ready & port.cmd.ready),
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fifo.sink.valid.eq(sink.valid & port.cmd.ready),
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fifo.sink.data.eq(sink.data)
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]
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self.comb += [
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port.wdata_valid.eq(fifo.source.valid),
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fifo.source.ready.eq(port.wdata_ready),
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port.wdata_we.eq(2**(port.dw//8)-1),
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port.wdata.eq(fifo.source.data)
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port.wdata.valid.eq(fifo.source.valid),
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fifo.source.ready.eq(port.wdata.ready),
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port.wdata.we.eq(2**(port.dw//8)-1),
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port.wdata.data.eq(fifo.source.data)
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]
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