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core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed)

This commit is contained in:
Florent Kermarrec 2018-10-01 11:18:39 +02:00
parent 70516c40bf
commit 8de1d91eac
3 changed files with 27 additions and 8 deletions
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7
litedram/common.py
View File

@ -99,6 +99,7 @@ def cmd_description(address_width):
("addr", address_width) ("addr", address_width)
] ]
def wdata_description(data_width, with_bank): def wdata_description(data_width, with_bank):
r = [ r = [
("data", data_width), ("data", data_width),
@ -116,7 +117,7 @@ def rdata_description(data_width, with_bank):
class LiteDRAMNativePort: class LiteDRAMNativePort:
def __init__(self, mode, address_width, data_width, clock_domain="sys", id=0): def __init__(self, mode, address_width, data_width, clock_domain="sys", id=0, with_bank=False):
self.mode = mode self.mode = mode
self.address_width = address_width self.address_width = address_width
self.data_width = data_width self.data_width = data_width
@ -126,8 +127,8 @@ class LiteDRAMNativePort:
self.lock = Signal() self.lock = Signal()
self.cmd = stream.Endpoint(cmd_description(address_width)) self.cmd = stream.Endpoint(cmd_description(address_width))
self.wdata = stream.Endpoint(wdata_description(data_width, True)) self.wdata = stream.Endpoint(wdata_description(data_width, with_bank))
self.rdata = stream.Endpoint(rdata_description(data_width, True)) self.rdata = stream.Endpoint(rdata_description(data_width, with_bank))
self.flush = Signal() self.flush = Signal()

24
litedram/frontend/crossbar.py
View File

@ -44,12 +44,24 @@ class LiteDRAMCrossbar(Module):
data_width = self.controller.data_width data_width = self.controller.data_width
# crossbar port # crossbar port
port = LiteDRAMNativePort(mode, self.rca_bits + self.bank_bits - self.rank_bits, self.controller.data_width, "sys", len(self.masters)) port = LiteDRAMNativePort(
mode=mode,
address_width=self.rca_bits + self.bank_bits - self.rank_bits,
data_width=self.controller.data_width,
clock_domain="sys",
id=len(self.masters),
with_bank=self.controller.settigns.with_reordering)
self.masters.append(port) self.masters.append(port)
# clock domain crossing # clock domain crossing
if clock_domain != "sys": if clock_domain != "sys":
new_port = LiteDRAMNativePort(mode, port.address_width, port.data_width, clock_domain, port.id) new_port = LiteDRAMNativePort(
mode=mode,
address_width=port.address_width,
data_width=port.data_width,
clock_domain=clock_domain,
id=port.id,
with_bank=self.controller.settings.with_reordering)
self.submodules += LiteDRAMNativePortCDC(new_port, port) self.submodules += LiteDRAMNativePortCDC(new_port, port)
port = new_port port = new_port
@ -59,7 +71,13 @@ class LiteDRAMCrossbar(Module):
addr_shift = -log2_int(data_width//self.controller.data_width) addr_shift = -log2_int(data_width//self.controller.data_width)
else: else:
addr_shift = log2_int(self.controller.data_width//data_width) addr_shift = log2_int(self.controller.data_width//data_width)
new_port = LiteDRAMNativePort(mode, port.address_width + addr_shift, data_width, clock_domain, port.id) new_port = LiteDRAMNativePort(
mode=mode,
address_width=port.address_width + addr_shift,
data_width=data_width,
clock_domain=clock_domain,
id=port.id,
with_bank=self.controller.settings.with_reordering)
self.submodules += ClockDomainsRenamer(clock_domain)(LiteDRAMNativePortConverter(new_port, port, reverse)) self.submodules += ClockDomainsRenamer(clock_domain)(LiteDRAMNativePortConverter(new_port, port, reverse))
port = new_port port = new_port

4
litedram/frontend/ecc.py
View File

@ -211,7 +211,7 @@ class LiteDRAMNativePortECC(Module, AutoCSR):
ecc_wdata = BufferizeEndpoints({"source": DIR_SOURCE})(ecc_wdata) ecc_wdata = BufferizeEndpoints({"source": DIR_SOURCE})(ecc_wdata)
self.submodules += ecc_wdata self.submodules += ecc_wdata
self.comb += [ self.comb += [
port_from.wdata.connect(ecc_wdata.sink), port_from.wdata.connect(ecc_wdata.sink, omit={"bank"}),
ecc_wdata.source.connect(port_to.wdata) ecc_wdata.source.connect(port_to.wdata)
] ]
@ -223,7 +223,7 @@ class LiteDRAMNativePortECC(Module, AutoCSR):
self.submodules += ecc_rdata self.submodules += ecc_rdata
self.comb += [ self.comb += [
ecc_rdata.enable.eq(self.enable.storage), ecc_rdata.enable.eq(self.enable.storage),
port_to.rdata.connect(ecc_rdata.sink), port_to.rdata.connect(ecc_rdata.sink, omit={"bank"}),
ecc_rdata.source.connect(port_from.rdata) ecc_rdata.source.connect(port_from.rdata)
] ]