modules: improve the way we define DDR4 banks/groups

litedram/modules.py

@@ -343,7 +343,9 @@ class AS4C256M16D3A(SDRAMModule):
 class EDY4016A(SDRAMModule):
     memtype = "DDR4"
     # geometry
-    nbanks = 2*4 # 2 groups of 4 banks
+    ngroupbanks = 4
+    ngroups     = 2
+    nbanks      = ngroups * ngroupbanks
     nrows       = 32768
     ncols       = 1024
     # timings
@@ -357,7 +359,9 @@ class EDY4016A(SDRAMModule):
 class MT40A1G8(SDRAMModule):
     memtype = "DDR4"
     # geometry
-    nbanks = 4*4 # 4 groups of 4 banks
+    ngroupbanks = 4
+    ngroups     = 4
+    nbanks      = ngroups * ngroupbanks
     nrows       = 65536
     ncols       = 1024
     # timings