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litedram
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init: add parentheses around #define with an expression

This commit is contained in:
Jędrzej Boczar 2021-07-23 14:44:15 +02:00
parent d20e8c763b
commit 91cae335e5
4 changed files with 6 additions and 6 deletions
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2
litedram/init.py
View File

@ -707,7 +707,7 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
r += "#define SDRAM_PHY_READ_LEVELING_CAPABLE\n"
# Define number of modules/delays/bitslips
r += "#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8\n"
r += "#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)\n"
if phytype in ["USDDRPHY", "USPDDRPHY"]:
r += "#define SDRAM_PHY_DELAYS 512\n"
r += "#define SDRAM_PHY_BITSLIPS 8\n"

2
test/reference/ddr3_init.h
View File

@ -28,7 +28,7 @@
#define SDRAM_PHY_WRITE_DQ_DQS_TRAINING_CAPABLE
#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
#define SDRAM_PHY_READ_LEVELING_CAPABLE
#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8
#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)
#define SDRAM_PHY_DELAYS 32
#define SDRAM_PHY_BITSLIPS 8

6
test/reference/ddr4_init.h
View File

@ -27,7 +27,7 @@
#define SDRAM_PHY_WRITE_LEVELING_CAPABLE
#define SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE
#define SDRAM_PHY_READ_LEVELING_CAPABLE
#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8
#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)
#define SDRAM_PHY_DELAYS 512
#define SDRAM_PHY_BITSLIPS 8
@ -65,7 +65,7 @@ static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase){
default: return 0;
}
}
static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
switch (phase) {
case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
@ -75,7 +75,7 @@ static inline unsigned long sdram_dfii_pix_rddata_addr(int phase){
default: return 0;
}
}
#define DDRX_MR_WRLVL_ADDRESS 1
#define DDRX_MR_WRLVL_RESET 769
#define DDRX_MR_WRLVL_BIT 7

2
test/reference/sdr_init.h
View File

@ -23,7 +23,7 @@
#define SDRAM_PHY_CWL 2
#define SDRAM_PHY_RDPHASE 0
#define SDRAM_PHY_WRPHASE 0
#define SDRAM_PHY_MODULES SDRAM_PHY_DATABITS/8
#define SDRAM_PHY_MODULES (SDRAM_PHY_DATABITS/8)
void cdelay(int i);